From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Yaroslav Bolyukin" <iam@lach.pw>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>
Cc: "Harry Wentland" <harry.wentland@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
"Rodrigo Siqueira" <siqueira@igalia.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Wayne Lin" <Wayne.Lin@amd.com>,
amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
"Yaroslav Bolyukin" <iam@lach.pw>
Subject: Re: [PATCH v7 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing
Date: Thu, 04 Dec 2025 14:11:20 +0200 [thread overview]
Message-ID: <b637bd5137f9ece93f4aec679949e567879e81be@intel.com> (raw)
In-Reply-To: <20251202110218.9212-6-iam@lach.pw>
On Tue, 02 Dec 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
> Other usages of block.rev bitfields were refactored to use FIELD_GET
> instead of bitwise ops.
>
> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_displayid_internal.h | 1 +
> drivers/gpu/drm/drm_edid.c | 3 ++-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
> index 724174b429f2..55f972d32847 100644
> --- a/drivers/gpu/drm/drm_displayid_internal.h
> +++ b/drivers/gpu/drm/drm_displayid_internal.h
> @@ -139,6 +139,7 @@ struct displayid_formula_timings_9 {
> u8 vrefresh;
> } __packed;
>
> +#define DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES GENMASK(6, 4)
> struct displayid_formula_timing_block {
> struct displayid_block base;
> struct displayid_formula_timings_9 timings[];
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index b28ff4bafb1d..be8715632b91 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6908,7 +6908,8 @@ static int add_displayid_formula_modes(struct drm_connector *connector,
> struct drm_display_mode *newmode;
> int num_modes = 0;
> bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING;
> - int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4);
> + int timing_size = 6 +
> + FIELD_GET(DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES, formula_block->base.rev);
>
> /* extended blocks are not supported yet */
> if (timing_size != 6)
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-12-04 12:11 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 11:02 [PATCH v7 0/7] VESA DisplayID fixed DSC BPP value support Yaroslav Bolyukin
2025-12-02 11:02 ` [PATCH v7 1/7] drm/edid: rename VESA block parsing functions to more generic name Yaroslav Bolyukin
2025-12-02 11:02 ` [PATCH v7 2/7] drm/edid: prepare for VESA vendor-specific data block extension Yaroslav Bolyukin
2025-12-02 11:02 ` [PATCH v7 3/7] drm/edid: MSO should only be used for non-eDP displays Yaroslav Bolyukin
2025-12-04 12:08 ` Jani Nikula
2025-12-02 11:02 ` [PATCH v7 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings Yaroslav Bolyukin
2025-12-04 12:11 ` Jani Nikula
2025-12-02 11:02 ` [PATCH v7 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing Yaroslav Bolyukin
2025-12-04 12:11 ` Jani Nikula [this message]
2025-12-02 11:02 ` [PATCH v7 6/7] drm/edid: parse DRM VESA dsc bpp target Yaroslav Bolyukin
2025-12-04 12:12 ` Jani Nikula
2025-12-02 11:02 ` [PATCH v7 7/7] drm/amd: use fixed dsc bits-per-pixel from edid Yaroslav Bolyukin
2025-12-29 2:25 ` Lin, Wayne
2026-01-08 20:45 ` [PATCH v7 0/7] VESA DisplayID fixed DSC BPP value support Yaroslav Bolyukin
2026-01-09 8:15 ` Jani Nikula
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