From: Andrew Lunn <andrew@lunn.ch>
To: Siddharth Vadapalli <s-vadapalli@ti.com>
Cc: Nishanth Menon <nm@ti.com>,
vigneshr@ti.com, kristo@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, danishanwar@ti.com,
r-gunasekaran@ti.com, srk@ti.com
Subject: Re: [PATCH v2] arm64: dts: ti: k3-am654-icssg2: Enable PHY interrupts for ICSSG2
Date: Sun, 17 Dec 2023 18:44:27 +0100 [thread overview]
Message-ID: <b0ecbd1f-354a-443a-849b-b00d2f1554d5@lunn.ch> (raw)
In-Reply-To: <6f1c1a59-cec0-46d1-8ecb-a82d9d444ccf@ti.com>
> Yes, you are right! Edge-Triggered interrupts shouldn't be shared. I missed
> noticing this. Thank you for pointing it out. Since the SoC only supports
> Edge-Triggered interrupts, I believe that the correct decision would be to use
> the interrupt for only one of the two PHYs, while leaving the other PHY in
> polled mode of operation which is the default.
No, if the PHY is using level interrupts, you need the SoC to use
level interrupts. Otherwise you are going to miss interrupts.
The board design is just broken and you cannot use interrupts at all.
Andrew
prev parent reply other threads:[~2023-12-17 17:44 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-13 8:02 Siddharth Vadapalli
2023-12-13 12:38 ` Nishanth Menon
2023-12-14 5:44 ` Siddharth Vadapalli
2023-12-14 12:17 ` Nishanth Menon
2023-12-14 13:50 ` Siddharth Vadapalli
2023-12-17 17:44 ` Andrew Lunn [this message]
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