* [PATCH 3/4] arm64: dts: qcom: Introduce Hawi SoC
2026-09-22 20:18 [PATCH 0/4] arm64: dts: qcom: Introduce Qualcomm Hawi platform device tree Mukesh Ojha
2026-09-22 20:18 ` [PATCH 1/4] dt-bindings: arm: cpus: Add Oryon PartNum 3 CPU compatibles Mukesh Ojha
2026-09-22 20:18 ` [PATCH 2/4] arm64: dts: qcom: hawi: Add header file for IPCC physical client IDs Mukesh Ojha
@ 2026-09-22 20:18 ` Mukesh Ojha
2026-09-23 10:41 ` Konrad Dybcio
2026-09-22 20:18 ` [PATCH 4/4] arm64: dts: qcom: hawi: Add base MTP board Mukesh Ojha
2026-09-24 1:06 ` (subset) [PATCH 0/4] arm64: dts: qcom: Introduce Qualcomm Hawi platform device tree Bjorn Andersson
4 siblings, 1 reply; 10+ messages in thread
From: Mukesh Ojha @ 2026-09-22 20:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Pieralisi, Bjorn Andersson, Konrad Dybcio, Abel Vesa
Cc: devicetree, linux-kernel, linux-arm-msm, Mukesh Ojha
Hawi is Snapdragon SoC from Qualcomm.
Features added in this commit:
- CPUs with PSCI idle states and cpufreq
- Interrupt-controller with PDC wakeup support
- Timers, TCSR Clock Controllers
- Reserved Shared memory
- GCC, RPMHCC, GPUCC, CAMCC and VideoCC
- TLMM
- Interconnect with CPU BWMONs
- QuP with UART
- SMMU
- RPMhPD
- UFS with Inline Crypto Engine
- LLCC
- Watchdog
- SD Card
- PCIe
- USB
- TSENS with thermal zones
- TRNG
- Remoteprocs (ADSP, CDSP, Modem, SoCCP)
- ADSP and CDSP with FastRPC support.
Written with help from Vivek Aknurwar (added interconnect, CAMCC nodes),
Xueyao An (added QUPv3 configuration), Fenglin Wu (added RPMhPD),
Palash Kambar (added UFS), Manivannan Sadhasivam (added ICE and TRNG),
Nitin Rawat (added SD Card), Matthew Leung (added PCIe), Ronak Raheja
(added USB), Dipa Ramesh Mantre (added TSENS and thermal zones), Lin Li
(added VideoCC) and Dongfang Zhao (added GPUCC).
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hawi.dtsi | 6847 ++++++++++++++++++++++++++++++++++++
1 file changed, 6847 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
new file mode 100644
index 000000000000..c7ae8133b9cd
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
@@ -0,0 +1,6847 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/clock/qcom,hawi-camcc.h>
+#include <dt-bindings/clock/qcom,hawi-gcc.h>
+#include <dt-bindings/clock/qcom,hawi-gpucc.h>
+#include <dt-bindings/clock/qcom,hawi-tcsrcc.h>
+#include <dt-bindings/clock/qcom,hawi-videocc.h>
+#include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h>
+#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+#include "hawi-ipcc.h"
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu6: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,oryon-3-0";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd6>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon-3-0";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd7>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,oryon-3-1";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd3>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
+ };
+
+ cpu0: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,oryon-3-2";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd0>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,oryon-3-1";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd4>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,oryon-3-2";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd1>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,oryon-3-1";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd5>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,oryon-3-2";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd2>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu3>;
+ };
+
+ core1 {
+ cpu = <&cpu4>;
+ };
+
+ core2 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ domain-idle-states {
+ cluster_cl5: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x01000054>;
+ entry-latency-us = <2150>;
+ exit-latency-us = <1983>;
+ min-residency-us = <17845>;
+ };
+
+ domain_ss3: domain-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x0200c354>;
+ entry-latency-us = <2800>;
+ exit-latency-us = <4400>;
+ min-residency-us = <19012>;
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cluster0_1_c4: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "retention";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <93>;
+ exit-latency-us = <129>;
+ min-residency-us = <1925>;
+ };
+
+ cluster2_c4: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "retention";
+ entry-latency-us = <172>;
+ exit-latency-us = <130>;
+ min-residency-us = <2356>;
+ arm,psci-suspend-param = <0x00000004>;
+ };
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-hawi", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x2000>;
+ interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ sram = <&minidump_config>;
+ };
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&pdp_tx>, <&pdp_rx>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_perf: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+ };
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,hawi-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,hawi-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory@a0000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0xa0000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ cpu_pd0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_1_c4>;
+ };
+
+ cpu_pd1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_1_c4>;
+ };
+
+ cpu_pd2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_1_c4>;
+ };
+
+ cpu_pd3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_1_c4>;
+ };
+
+ cpu_pd4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_1_c4>;
+ };
+
+ cpu_pd5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_1_c4>;
+ };
+
+ cpu_pd6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster2_c4>;
+ };
+
+ cpu_pd7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster2_c4>;
+ };
+
+ cluster_pd: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_cl5>,
+ <&domain_ss3>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cpucp_slc_mem_sub: cpucp@81230000 {
+ reg = <0x0 0x81230000 0x0 0x1000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x100000>;
+ no-map;
+ };
+
+ smem_mem: smem@82700000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x82700000 0x0 0x400000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ dsm_partition_1_mem: dsm-partition-1@83500000 {
+ reg = <0x0 0x83500000 0x0 0x5180000>;
+ no-map;
+ };
+
+ dsm_partition_2_mem: dsm-partition-2@88680000 {
+ reg = <0x0 0x88680000 0x0 0x1700000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@89e00000 {
+ reg = <0x0 0x89e00000 0x0 0xe600000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb@98400000 {
+ reg = <0x0 0x98400000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@99580000 {
+ reg = <0x0 0x99580000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@99590000 {
+ reg = <0x0 0x99590000 0x0 0xc000>;
+ no-map;
+ };
+
+ gpu_microcode_mem: gpu-microcode@9959c000 {
+ reg = <0x0 0x9959c000 0x0 0x4000>;
+ no-map;
+ };
+
+ camera_mem: camera@99600000 {
+ reg = <0x0 0x99600000 0x0 0x800000>;
+ no-map;
+ };
+
+ camera_2_mem: camera-2@99e00000 {
+ reg = <0x0 0x99e00000 0x0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video@9a600000 {
+ reg = <0x0 0x9a600000 0x0 0x800000>;
+ no-map;
+ };
+
+ cvp_mem: cvp@9ae00000 {
+ reg = <0x0 0x9ae00000 0x0 0x800000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@9b900000 {
+ reg = <0x0 0x9b900000 0x0 0x2000000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb@9d900000 {
+ reg = <0x0 0x9d900000 0x0 0x80000>;
+ no-map;
+ };
+
+ dcp_dtb_mem: dcp-dtb@a0000000 {
+ reg = <0x0 0xa0000000 0x0 0x80000>;
+ no-map;
+ };
+
+ dcp_mem: dcp@a0080000 {
+ reg = <0x0 0xa0080000 0x0 0x400000>;
+ no-map;
+ };
+
+ soccp_mem: soccp@a0480000 {
+ reg = <0x0 0xa0480000 0x0 0x500000>;
+ no-map;
+ };
+
+ soccp_dtb_mem: soccp-dtb@a0980000 {
+ reg = <0x0 0xa0980000 0x0 0x40000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 {
+ reg = <0x0 0xa1380000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi@a1400000 {
+ reg = <0x0 0xa1400000 0x0 0x5f00000>;
+ no-map;
+ };
+
+ mpss_crashdump_overlay_mem: mpss-crashdump-overlay@bd500000 {
+ reg = <0x0 0xbd500000 0x0 0xf00000>;
+ no-map;
+ };
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <443>, <429>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <94>, <432>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ smp2p_cdsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_MPROC_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <435>, <428>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ smp2p_modem_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_modem_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-soccp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <617>, <616>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <19>;
+
+ soccp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ soccp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+ ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,hawi-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>,
+ <&pcie0_phy>,
+ <&pcie1_phy>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
+ <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,hawi-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00800000 0x0 0x60000>;
+
+ interrupts = <GIC_ESPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 912 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 913 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 914 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 915 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 916 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 917 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 918 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x1f>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x36 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_2: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x008c0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0x23 0x0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c8: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 417 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi8: spi@880000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 417 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart8: serial@880000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 417 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart8_default>, <&qup_uart8_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c9: i2c@884000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00884000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 418 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi9: spi@884000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00884000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 418 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart9: serial@884000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00884000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 418 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart9_default>, <&qup_uart9_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c10: i2c@888000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00888000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 419 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi10: spi@888000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00888000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 419 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart10: serial@888000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00888000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 419 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart10_default>, <&qup_uart10_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c11: i2c@88c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x0088c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 420 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi11: spi@88c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x0088c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 420 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart11: serial@88c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x0088c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 420 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c12: i2c@890000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00890000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 421 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart12: serial@890000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00890000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 421 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart12_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ i2c_master_hub: geniqup@9c0000 {
+ compatible = "qcom,geni-se-i2c-master-hub";
+ reg = <0x0 0x009c0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
+ clock-names = "s-ahb";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c_hub_0: i2c@980000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00980000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 528 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_1: i2c@984000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00984000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 529 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_2: i2c@988000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00988000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 530 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_3: i2c@98c000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x0098c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 531 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_4: i2c@990000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00990000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 532 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,hawi-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00a00000 0x0 0x60000>;
+
+ interrupts = <GIC_ESPI 900 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 901 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 902 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 903 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 904 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 905 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 906 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 907 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 908 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 909 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 910 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 911 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 944 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 945 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 946 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 947 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <16>;
+ dma-channel-mask = <0x7f>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0xb6 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0xa3 0x0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c0: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 892 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi0: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 892 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart0: serial@a80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 892 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart0_default>, <&qup_uart0_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c1: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 893 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi1: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 893 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 893 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart1_default>, <&qup_uart1_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 894 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi2: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 894 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 894 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart2_default>, <&qup_uart2_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 895 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi3: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 895 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart3: serial@a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 895 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart3_default>, <&qup_uart3_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a90000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 896 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi4: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a90000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 896 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart4: serial@a90000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a90000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 896 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c5: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 897 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi5: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 897 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart5: serial@a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 897 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c6: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a98000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 898 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi6: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a98000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 898 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart6: serial@a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a98000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 898 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ uart7: serial@a9c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 899 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ remoteproc_soccp: remoteproc@d00000 {
+ compatible = "qcom,hawi-soccp-pas", "qcom,kaanapali-soccp-pas";
+ reg = <0x0 0x00d00000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_ESPI 231 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "pong";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ memory-region = <&soccp_mem>,
+ <&soccp_dtb_mem>;
+
+ qcom,smem-states = <&soccp_smp2p_out 0>,
+ <&soccp_smp2p_out 8>;
+ qcom,smem-state-names = "stop",
+ "ping";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ qcom,remote-pid = <19>;
+ label = "soccp";
+ };
+ };
+
+ aggre_noc: interconnect@f00000 {
+ compatible = "qcom,hawi-aggre1-noc";
+ reg = <0x0 0x00f00000 0x0 0x54400>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&rpmhcc RPMH_IPA_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ usb_1_hsphy: phy@fe3000 {
+ compatible = "qcom,hawi-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy";
+ reg = <0x0 0x00fe3000 0x0 0x29c>;
+
+ clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_dp_qmpphy: phy@fe8000 {
+ compatible = "qcom,hawi-qmp-usb3-dp-phy";
+ reg = <0x0 0x00fe8000 0x0 0x4000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_USB3_CLKREF_EN>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy",
+ "common";
+
+ power-domains = <&gcc GCC_USB3_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ orientation-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_dp_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_dp_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_dp_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
+ };
+
+ rng@10c3000 {
+ compatible = "qcom,hawi-trng", "qcom,trng";
+ reg = <0x0 0x010c3000 0x0 0x1000>;
+ };
+
+ ipcc: mailbox@1106000 {
+ compatible = "qcom,hawi-ipcc", "qcom,ipcc";
+ reg = <0x0 0x01106000 0x0 0x1000>;
+
+ interrupts = <GIC_ESPI 310 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ #mbox-cells = <2>;
+ };
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,hawi-cnoc-main";
+ reg = <0x0 0x01500000 0x0 0x20000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,hawi-system-noc";
+ reg = <0x0 0x01680000 0x0 0x20080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ pcie_anoc: interconnect@16c0000 {
+ compatible = "qcom,hawi-pcie-anoc";
+ reg = <0x0 0x016c0000 0x0 0x12400>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+ };
+
+ cambistmclkcc: clock-controller@1760000 {
+ compatible = "qcom,hawi-cambistmclkcc",
+ "qcom,kaanapali-cambistmclkcc";
+ reg = <0x0 0x01760000 0x0 0x6000>;
+
+ clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MX>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mmss_noc: interconnect@1780000 {
+ compatible = "qcom,hawi-mmss-noc";
+ reg = <0x0 0x01780000 0x0 0x5f800>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpi_dma3: dma-controller@1900000 {
+ compatible = "qcom,hawi-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x01900000 0x0 0x60000>;
+
+ interrupts = <GIC_ESPI 652 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 653 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 654 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 655 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 656 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 657 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 658 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 659 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 660 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 661 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 662 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 663 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x1f>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0xd6 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_3: geniqup@19c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x019c0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0xc3 0x0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c13: i2c@1980000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01980000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 437 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart13: serial@1980000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x01980000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 437 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart13_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c14: i2c@1984000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01984000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 647 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma3 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi14: spi@1984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01984000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 647 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma3 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma3 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart14: serial@1984000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x01984000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 647 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c15: i2c@1988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01988000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 648 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma3 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi15: spi@1988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01988000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 648 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma3 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma3 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart15: serial@1988000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x01988000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 648 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart15_default>, <&qup_uart15_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c16: i2c@198c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x0198c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 649 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma3 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c16_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi16: spi@198c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x0198c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 649 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma3 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma3 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart16: serial@198c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x0198c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 649 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart16_default>, <&qup_uart16_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c17: i2c@1990000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01990000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 650 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma3 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c17_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi17: spi@1990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01990000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 650 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma3 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma3 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart17: serial@1990000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x01990000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 650 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart17_default>, <&qup_uart17_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ uart18: serial@1994000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x01994000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 651 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP3_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart18_default>, <&qup_uart18_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ gpi_dma4: dma-controller@1a00000 {
+ compatible = "qcom,hawi-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x01a00000 0x0 0x60000>;
+
+ interrupts = <GIC_ESPI 568 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 569 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 570 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 571 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 572 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 573 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 574 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 575 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 577 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 578 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 579 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x1f>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x136 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_4: geniqup@1ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x01ac0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_4_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_4_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0x123 0x0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c19: i2c@1a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a80000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 920 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma4 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma4 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c19_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi19: spi@1a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01a80000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 920 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma4 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma4 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart19: serial@1a80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x01a80000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 920 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart19_default>, <&qup_uart19_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c20: i2c@1a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a84000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 921 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma4 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma4 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c20_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi20: spi@1a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01a84000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 921 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma4 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma4 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart20: serial@1a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x01a84000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 921 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart20_default>, <&qup_uart20_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c21: i2c@1a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a88000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 922 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma4 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma4 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c21_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi21: spi@1a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x01a88000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 922 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma4 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma4 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart21: serial@1a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x01a88000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 922 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart21_default>, <&qup_uart21_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c22: i2c@1a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 923 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma4 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma4 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c22_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart22: serial@1a8c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x01a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 923 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart22_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c23: i2c@1a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x01a90000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 924 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma4 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma4 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c23_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart23: serial@1a90000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x01a90000 0x0 0x4000>;
+
+ interrupts = <GIC_ESPI 924 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP4_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart23_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ pcie0: pcie@1c00000 {
+ device_type = "pci";
+ compatible = "qcom,hawi-pcie";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf1d>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x1000>,
+ <0x0 0x40100000 0x0 0x100000>,
+ <0x0 0x01c03000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>;
+
+ interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ resets = <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+
+ operating-points-v2 = <&pcie0_opp_table>;
+
+ iommu-map = <0 &apps_smmu 0x1000 0x1>,
+ <0x100 &apps_smmu 0x1001 0x1>;
+
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ #interrupt-cells = <1>;
+
+ msi-map = <0x0 &gic_its 0x1000 0x1>,
+ <0x100 &gic_its 0x1001 0x1>;
+ msi-map-mask = <0xff00>;
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ dma-coherent;
+
+ status = "disabled";
+
+ pcie0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* 2.5 GT/s */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* 5.0 GT/s */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* 8.0 GT/s */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* 10 GT/s */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* 16 GT/s */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1969000 1>;
+ };
+ };
+
+ pcie0_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ phys = <&pcie0_phy>;
+ };
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,hawi-qmp-gen3x2-pcie-phy";
+ reg = <0x0 0x01c06000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
+ <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>,
+ <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie1: pcie@1c18000 {
+ device_type = "pci";
+ compatible = "qcom,hawi-pcie";
+ reg = <0x0 0x01c18000 0x0 0x3000>,
+ <0x0 0x64000000 0x0 0xf1d>,
+ <0x0 0x64000f20 0x0 0xa8>,
+ <0x0 0x64001000 0x0 0x1000>,
+ <0x0 0x64100000 0x0 0x100000>,
+ <0x0 0x01c1b000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
+ <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x1bd00000>;
+
+ interrupts = <GIC_ESPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ resets = <&gcc GCC_PCIE_1_BCR>,
+ <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ power-domains = <&gcc GCC_PCIE_1_GDSC>;
+
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+
+ operating-points-v2 = <&pcie1_opp_table>;
+
+ iommu-map = <0 &apps_smmu 0x1080 0x1>,
+ <0x100 &apps_smmu 0x1081 0x1>;
+
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_ESPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_ESPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_ESPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ #interrupt-cells = <1>;
+
+ msi-map = <0x0 &gic_its 0x1080 0x1>,
+ <0x100 &gic_its 0x1081 0x1>;
+ msi-map-mask = <0xff00>;
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ dma-coherent;
+
+ status = "disabled";
+
+ pcie1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* 2.5 GT/s */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* 5.0 GT/s */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* 8.0 GT/s */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* 16 GT/s */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <1969000 1>;
+ };
+ };
+
+ pcie1_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ phys = <&pcie1_phy>;
+ };
+ };
+
+ pcie1_phy: phy@1c1e000 {
+ compatible = "qcom,hawi-qmp-gen4x1-pcie-phy";
+ reg = <0x0 0x01c1e000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&tcsrcc TCSR_PCIE_1_CLKREF_EN>,
+ <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_DIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>,
+ <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ power-domains = <&gcc GCC_PCIE_1_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie1_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ sdhc_2: mmc@1c44000 {
+ compatible = "qcom,hawi-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x01c44000 0x0 0x1000>;
+
+ interrupts = <GIC_ESPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+
+ clock-names = "iface", "core", "xo";
+
+ interconnects = <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ iommus = <&apps_smmu 0x140 0x0>;
+ dma-coherent;
+
+ resets = <&gcc GCC_SDCC2_BCR>;
+
+ bus-width = <4>;
+ max-sd-hs-hz = <37500000>;
+
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-peak-kBps = <160000 100000>;
+ opp-avg-kBps = <50000 0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ opp-peak-kBps = <200000 120000>;
+ opp-avg-kBps = <104000 0>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+
+ };
+
+ ufs_mem_phy: phy@1d80000 {
+ compatible = "qcom,hawi-qmp-ufs-phy";
+ reg = <0x0 0x01d80000 0x0 0x4000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_UFS_CLKREF_EN>;
+
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,hawi-ufshc",
+ "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+
+ interrupts = <GIC_ESPI 329 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_5_CORE_CLK>,
+ <&rpmhcc RPMH_LN_BB_CLK3>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+
+ operating-points-v2 = <&ufshc_opp_table>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ interconnects = <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "ufs-ddr",
+ "cpu-ufs";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ iommus = <&apps_smmu 0x60 0x0>;
+ dma-coherent;
+
+ lanes-per-direction = <2>;
+ limit-hs-gear = <5>;
+
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+
+ qcom,ice = <&ice>;
+
+ #reset-cells = <1>;
+
+ status = "disabled";
+
+ ufshc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <100000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-450000000 {
+ opp-hz = /bits/ 64 <403000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <403000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ ice: crypto@1d88000 {
+ compatible = "qcom,hawi-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x01d88000 0x0 0x18000>;
+
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>;
+ clock-names = "core",
+ "iface";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ };
+
+ videocc: clock-controller@20f0000 {
+ compatible = "qcom,hawi-videocc";
+ reg = <0x0 0x020f0000 0x0 0x10000>;
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs_d2>,
+ <&rpmhpd_opp_low_svs_d2>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ apps_smmu: iommu@2e00000 {
+ compatible = "qcom,hawi-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x02e00000 0x0 0x100000>;
+
+ interrupts = <GIC_ESPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 379 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 391 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 392 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 461 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 482 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 483 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 485 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 771 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 487 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 489 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 754 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 755 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 757 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 760 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 761 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 552 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 553 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 554 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 555 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 556 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 557 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 558 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 559 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 560 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 561 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 562 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 563 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 564 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 565 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 566 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 567 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 928 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 929 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 930 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 931 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 932 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 933 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 934 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 935 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 936 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 937 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 938 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 939 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 940 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 941 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 942 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ dma-coherent;
+ };
+
+ stdst_noc: interconnect@3000000 {
+ compatible = "qcom,hawi-stdst-main";
+ reg = <0x0 0x03000000 0x0 0x10000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ config_noc: interconnect@3010000 {
+ compatible = "qcom,hawi-stdst-cfg";
+ reg = <0x0 0x03010000 0x0 0xb1000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ tcsr: syscon@3a70000 {
+ compatible = "qcom,hawi-tcsr", "syscon";
+ reg = <0x0 0x03a70000 0x0 0x10000>;
+ };
+
+ tcsr_mutex: hwlock@3ad3000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x03ad3000 0x0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsrcc: clock-controller@3b13040 {
+ compatible = "qcom,hawi-tcsrcc", "syscon";
+ reg = <0x0 0x03b13040 0x0 0x50>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gxclkctl: clock-controller@3d64000 {
+ compatible = "qcom,hawi-gxclkctl",
+ "qcom,kaanapali-gxclkctl";
+ reg = <0x0 0x03d64000 0x0 0x6000>;
+
+ power-domains = <&rpmhpd RPMHPD_GFX>,
+ <&rpmhpd RPMHPD_GMXC>,
+ <&gpucc GPU_CC_CX_GDSC>;
+
+ #power-domain-cells = <1>;
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,hawi-gpucc";
+ reg = <0x0 0x03d90000 0x0 0x9800>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>,
+ <&rpmhpd RPMHPD_GMXC>;
+ required-opps = <&rpmhpd_opp_low_svs_d3>,
+ <&rpmhpd_opp_low_svs_d3>,
+ <&rpmhpd_opp_low_svs_d3>;
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,hawi-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_ESPI 738 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 742 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 743 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 744 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 745 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 746 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 747 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 748 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 749 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 750 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 751 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 752 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 540 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 638 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 639 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 640 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 724 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 726 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 729 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 730 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 731 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 733 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 734 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 764 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
+ clock-names = "hlos";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ dma-coherent;
+ };
+
+ remoteproc_mpss: remoteproc@4000000 {
+ compatible = "qcom,hawi-mpss-pas", "qcom,sm8650-mpss-pas";
+ reg = <0x0 0x04000000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_ESPI 328 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MSS>;
+ power-domain-names = "cx",
+ "mss";
+
+ memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&dsm_partition_1_mem>,
+ <&dsm_partition_2_mem>, <&mpss_crashdump_overlay_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_modem_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ qcom,remote-pid = <1>;
+ label = "mpss";
+ };
+ };
+
+ remoteproc_adsp: remoteproc@7000000 {
+ compatible = "qcom,hawi-adsp-pas", "qcom,sm8550-adsp-pas";
+ reg = <0x0 0x07000000 0x0 0x10000>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx",
+ "lmx";
+
+ memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ qcom,remote-pid = <2>;
+ label = "lpass";
+
+ fastrpc {
+ compatible = "qcom,hawi-fastrpc", "qcom,kaanapali-fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+
+ iommus = <&apps_smmu 0x0c03 0x80>,
+ <&apps_smmu 0x0c43 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+
+ iommus = <&apps_smmu 0x0c04 0x80>,
+ <&apps_smmu 0x0c44 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+
+ iommus = <&apps_smmu 0x0c05 0x80>,
+ <&apps_smmu 0x0c45 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+
+ iommus = <&apps_smmu 0x0c06 0x80>,
+ <&apps_smmu 0x0c46 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+
+ iommus = <&apps_smmu 0x0c07 0x80>,
+ <&apps_smmu 0x0c47 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+
+ iommus = <&apps_smmu 0x0c08 0x80>,
+ <&apps_smmu 0x0c48 0x20>;
+ dma-coherent;
+ };
+ };
+ };
+ };
+
+ lpass_lpiaon_noc: interconnect@7c00000 {
+ compatible = "qcom,hawi-lpass-lpiaon-noc";
+ reg = <0x0 0x07c00000 0x0 0x19080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ lpass_lpicx_noc: interconnect@7c20000 {
+ compatible = "qcom,hawi-lpass-lpicx-noc";
+ reg = <0x0 0x07c20000 0x0 0x46080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ lpass_ag_noc: interconnect@8f40000 {
+ compatible = "qcom,hawi-lpass-ag-noc";
+ reg = <0x0 0x08f40000 0x0 0xc080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ camcc: clock-controller@956d000 {
+ compatible = "qcom,hawi-camcc";
+ reg = <0x0 0x0956d000 0x0 0x80000>;
+
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+
+ interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ usb_1: usb@a600000 {
+ compatible = "qcom,hawi-dwc3", "qcom,snps-dwc3";
+ reg = <0x0 0x0a600000 0x0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_STARDUSTNOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_ESPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_ESPI 194 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_ESPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ interconnects = <&aggre_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_USB3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+ iommus = <&apps_smmu 0x40 0x0>;
+
+ phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy", "usb3-phy";
+
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,usb2-gadget-lpm-disable;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,is-utmi-l1-suspend;
+ snps,usb3_lpm_capable;
+ snps,usb2-lpm-disable;
+ snps,has-lpm-erratum;
+ tx-fifo-resize;
+ dma-coherent;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,hawi-pdc", "qcom,pdc";
+ reg = <0x0 0x0b220000 0x0 0x10000>,
+ <0x0 0x179600f0 0x0 0xf4>;
+
+ qcom,pdc-ranges = <0 256 196>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ tsens0: thermal-sensor@c22b000 {
+ compatible = "qcom,hawi-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22b000 0x0 0x1000>,
+ <0x0 0x0c222000 0x0 0x1000>;
+ interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <12>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c22c000 {
+ compatible = "qcom,hawi-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22c000 0x0 0x1000>,
+ <0x0 0x0c223000 0x0 0x1000>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <7>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens2: thermal-sensor@c22d000 {
+ compatible = "qcom,hawi-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22d000 0x0 0x1000>,
+ <0x0 0x0c224000 0x0 0x1000>;
+ interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <6>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens3: thermal-sensor@c22e000 {
+ compatible = "qcom,hawi-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22e000 0x0 0x1000>,
+ <0x0 0x0c225000 0x0 0x1000>;
+ interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <9>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens4: thermal-sensor@c22f000 {
+ compatible = "qcom,hawi-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c22f000 0x0 0x1000>,
+ <0x0 0x0c226000 0x0 0x1000>;
+ interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <9>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens5: thermal-sensor@c230000 {
+ compatible = "qcom,hawi-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c230000 0x0 0x1000>,
+ <0x0 0x0c227000 0x0 0x1000>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens6: thermal-sensor@c231000 {
+ compatible = "qcom,hawi-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c231000 0x0 0x1000>,
+ <0x0 0x0c228000 0x0 0x1000>;
+ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <8>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,hawi-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0x0 0x0c300000 0x0 0x400>;
+
+ interrupts-extended = <&ipcc IPCC_MPROC_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
+ arbiter@c400000 {
+ compatible = "qcom,hawi-spmi-pmic-arb",
+ "qcom,glymur-spmi-pmic-arb";
+ reg = <0x0 0x0c400000 0x0 0x3000>,
+ <0x0 0xc900000 0x0 0x400000>,
+ <0x0 0xc4c0000 0x0 0x400000>,
+ <0x0 0xc403000 0x0 0x8000>;
+ reg-names = "core",
+ "chnls",
+ "obsrvr",
+ "chnl_map";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ qcom,channel = <0>;
+ qcom,ee = <0>;
+
+ spmi_bus0: spmi@c426000 {
+ reg = <0x0 0x0c426000 0x0 0x4000>,
+ <0x0 0xc8c0000 0x0 0x10000>,
+ <0x0 0xc42a000 0x0 0x8000>;
+ reg-names = "cnfg",
+ "intr",
+ "chnl_owner";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ spmi_bus1: spmi@c437000 {
+ reg = <0x0 0x0c437000 0x0 0x4000>,
+ <0x0 0xc8d0000 0x0 0x10000>,
+ <0x0 0xc43b000 0x0 0x8000>;
+ reg-names = "cnfg",
+ "intr",
+ "chnl_owner";
+ interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,hawi-tlmm";
+ reg = <0x0 0x0f100000 0x0 0x102000>;
+ interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 227>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ wakeup-parent = <&pdc>;
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio0", "gpio1";
+ function = "qup2_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart8_cts_rts: qup-uart8-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio0", "gpio1";
+ function = "qup2_se0";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart8_default: qup-uart8-default-state {
+ /* TX, RX */
+ pins = "gpio2", "gpio3";
+ function = "qup2_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio3";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio4", "gpio5", "gpio6";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart9_cts_rts: qup-uart9-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio4", "gpio5";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart9_default: qup-uart9-default-state {
+ /* TX, RX */
+ pins = "gpio6", "gpio7";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi9_cs: qup-spi9-cs-state {
+ pins = "gpio7";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c14_data_clk: qup-i2c14-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio8", "gpio9";
+ function = "qup3_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup3_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio8", "gpio9";
+ function = "qup3_se1";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart14_default: qup-uart14-default-state {
+ /* TX, RX */
+ pins = "gpio10", "gpio11";
+ function = "qup3_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi14_cs: qup-spi14-cs-state {
+ pins = "gpio11";
+ function = "qup3_se1";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio12", "gpio13";
+ function = "qup3_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio12", "gpio13", "gpio14";
+ function = "qup3_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart15_cts_rts: qup-uart15-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio12", "gpio13";
+ function = "qup3_se2";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart15_default: qup-uart15-default-state {
+ /* TX, RX */
+ pins = "gpio14", "gpio15";
+ function = "qup3_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi15_cs: qup-spi15-cs-state {
+ pins = "gpio15";
+ function = "qup3_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c16_data_clk: qup-i2c16-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio16", "gpio17";
+ function = "qup3_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi16_data_clk: qup-spi16-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio16", "gpio17", "gpio18";
+ function = "qup3_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart16_cts_rts: qup-uart16-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio16", "gpio17";
+ function = "qup3_se3";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart16_default: qup-uart16-default-state {
+ /* TX, RX */
+ pins = "gpio18", "gpio19";
+ function = "qup3_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi16_cs: qup-spi16-cs-state {
+ pins = "gpio19";
+ function = "qup3_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c17_data_clk: qup-i2c17-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio20", "gpio21";
+ function = "qup3_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi17_data_clk: qup-spi17-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio20", "gpio21", "gpio22";
+ function = "qup3_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart17_cts_rts: qup-uart17-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio20", "gpio21";
+ function = "qup3_se4";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart17_default: qup-uart17-default-state {
+ /* TX, RX */
+ pins = "gpio22", "gpio23";
+ function = "qup3_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi17_cs: qup-spi17-cs-state {
+ pins = "gpio23";
+ function = "qup3_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart18_cts_rts: qup-uart18-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio24", "gpio25";
+ function = "qup3_se5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart18_default: qup-uart18-default-state {
+ /* TX, RX */
+ pins = "gpio26", "gpio27";
+ function = "qup3_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c20_data_clk: qup-i2c20-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio28", "gpio29";
+ function = "qup4_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi20_data_clk: qup-spi20-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio28", "gpio29", "gpio30";
+ function = "qup4_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart20_cts_rts: qup-uart20-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio28", "gpio29";
+ function = "qup4_se1";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart20_default: qup-uart20-default-state {
+ /* TX, RX */
+ pins = "gpio30", "gpio31";
+ function = "qup4_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi20_cs: qup-spi20-cs-state {
+ pins = "gpio31";
+ function = "qup4_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c21_data_clk: qup-i2c21-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio32", "gpio33";
+ function = "qup4_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi21_data_clk: qup-spi21-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio32", "gpio33", "gpio34";
+ function = "qup4_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart21_cts_rts: qup-uart21-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio32", "gpio33";
+ function = "qup4_se2";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart21_default: qup-uart21-default-state {
+ /* TX, RX */
+ pins = "gpio34", "gpio35";
+ function = "qup4_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi21_cs: qup-spi21-cs-state {
+ pins = "gpio35";
+ function = "qup4_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio36", "gpio37";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio36", "gpio37", "gpio38";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart4_cts_rts: qup-uart4-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio36", "gpio37";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart4_default: qup-uart4-default-state {
+ /* TX, RX */
+ pins = "gpio38", "gpio39";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi4_cs: qup-spi4-cs-state {
+ pins = "gpio39";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio40", "gpio41";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio40", "gpio41", "gpio42";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart2_cts_rts: qup-uart2-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio40", "gpio41";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart2_default: qup-uart2-default-state {
+ /* TX, RX */
+ pins = "gpio42", "gpio43";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio43";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio44", "gpio45";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio44", "gpio45", "gpio46";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart3_cts_rts: qup-uart3-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio44", "gpio45";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart3_default: qup-uart3-default-state {
+ /* TX, RX */
+ pins = "gpio46", "gpio47";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio47";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c19_data_clk: qup-i2c19-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio48", "gpio49";
+ function = "qup4_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi19_data_clk: qup-spi19-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio48", "gpio49", "gpio50";
+ function = "qup4_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart19_cts_rts: qup-uart19-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio48", "gpio49";
+ function = "qup4_se0";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart19_default: qup-uart19-default-state {
+ /* TX, RX */
+ pins = "gpio50", "gpio51";
+ function = "qup4_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi19_cs: qup-spi19-cs-state {
+ pins = "gpio51";
+ function = "qup4_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio52", "gpio53";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart5_cts_rts: qup-uart5-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio52", "gpio53";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart5_default: qup-uart5-default-state {
+ /* TX, RX */
+ pins = "gpio54", "gpio55";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio55";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ card-detect-pins {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ card-detect-pins {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio56", "gpio57";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio56", "gpio57", "gpio58";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart6_cts_rts: qup-uart6-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio56", "gpio57";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart6_default: qup-uart6-default-state {
+ /* TX, RX */
+ pins = "gpio58", "gpio59";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio59";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart7_default: qup-uart7-state {
+ /* TX, RX */
+ pins = "gpio62", "gpio63";
+ function = "qup1_se7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio64", "gpio65";
+ function = "qup3_se0_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart13_default: qup-uart13-default-state {
+ /* TX, RX */
+ pins = "gpio64", "gpio65";
+ function = "qup3_se0_23";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c0_data_clk: hub-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio66", "gpio67";
+ function = "i2chub0_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c2_data_clk: hub-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio68", "gpio69";
+ function = "i2chub0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c3_data_clk: hub-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio70", "gpio71";
+ function = "i2chub0_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c4_data_clk: hub-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio72", "gpio73";
+ function = "i2chub0_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio74", "gpio75";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio74", "gpio75", "gpio76";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart1_cts_rts: qup-uart1-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio74", "gpio75";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart1_default: qup-uart1-default-state {
+ /* TX, RX */
+ pins = "gpio76", "gpio77";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio77";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ hub_i2c1_data_clk: hub-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio78", "gpio79";
+ function = "i2chub0_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio80", "gpio83";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio80", "gpio83", "gpio82";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart0_cts_rts: qup-uart0-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio80", "gpio83";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio81";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart0_default: qup-uart0-default-state {
+ /* TX, RX */
+ pins = "gpio82", "gpio81";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c22_data_clk: qup-i2c22-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio121", "gpio84";
+ function = "qup4_se3_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart22_default: qup-uart22-default-state {
+ /* TX, RX */
+ pins = "gpio121", "gpio84";
+ function = "qup4_se3_23";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie0_default_state: pcie0-default-state {
+ perst-n-pins {
+ pins = "gpio102";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ clkreq-n-pins {
+ pins = "gpio103";
+ function = "pcie0_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-n-pins {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio117", "gpio118";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio117", "gpio118", "gpio119";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart10_cts_rts: qup-uart10-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio117", "gpio118";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart10_default: qup-uart10-default-state {
+ /* TX, RX */
+ pins = "gpio119", "gpio120";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio120";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio122", "gpio123";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio122", "gpio123", "gpio124";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart11_cts_rts: qup-uart11-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio122", "gpio123";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart11_default: qup-uart11-default-state {
+ /* TX, RX */
+ pins = "gpio124", "gpio125";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio125";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c23_data_clk: qup-i2c23-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio161", "gpio162";
+ function = "qup4_se4_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart23_default: qup-uart23-default-state {
+ /* TX, RX */
+ pins = "gpio161", "gpio162";
+ function = "qup4_se4_23";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio208", "gpio209";
+ function = "qup2_se4_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart12_default: qup-uart12-default-state {
+ /* TX, RX */
+ pins = "gpio208", "gpio209";
+ function = "qup2_se4_23";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie1_default_state: pcie1-default-state {
+ perst-n-pins {
+ pins = "gpio220";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ clkreq-n-pins {
+ pins = "gpio221";
+ function = "pcie1_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-n-pins {
+ pins = "gpio222";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ sram@14680000 {
+ compatible = "qcom,hawi-imem", "mmio-sram";
+ reg = <0x0 0x14680000 0x0 0x1000>;
+ ranges = <0x0 0x0 0x14680000 0x1000>;
+
+ no-memory-wc;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ minidump_config: minidump-sram@1c {
+ reg = <0x1c 0x4>;
+ };
+
+ pil-sram@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
+ intc: interrupt-controller@17000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x17000000 0x0 0x10000>,
+ <0x0 0x17080000 0x0 0x200000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic_its: msi-controller@17040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x17040000 0x0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ watchdog@17600000 {
+ compatible = "qcom,apss-wdt-hawi", "qcom,kpss-wdt";
+ reg = <0x0 0x17600000 0x0 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pdp0_mbox: mailbox@17610000 {
+ compatible = "qcom,hawi-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
+ reg = <0x0 0x17610000 0x0 0x8000>,
+ <0x0 0x19990000 0x0 0x8000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
+ timer@17810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x17810000 0x0 0x1000>;
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x0 0x20000000>;
+
+ frame@17811000 {
+ reg = <0x0 0x17811000 0x1000>,
+ <0x0 0x17812000 0x1000>;
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ frame@17813000 {
+ reg = <0x0 0x17813000 0x1000>;
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ frame@17815000 {
+ reg = <0x0 0x17815000 0x1000>;
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ frame@17817000 {
+ reg = <0x0 0x17817000 0x1000>;
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ frame@17819000 {
+ reg = <0x0 0x17819000 0x1000>;
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ frame@1781b000 {
+ reg = <0x0 0x1781b000 0x1000>;
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ frame@1781d000 {
+ reg = <0x0 0x1781d000 0x1000>;
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@18900000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x18900000 0x0 0x10000>,
+ <0x0 0x18910000 0x0 0x10000>,
+ <0x0 0x18920000 0x0 0x10000>;
+ reg-names = "drv-0",
+ "drv-1",
+ "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&cluster_pd>;
+ label = "apps_rsc";
+
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 3>,
+ <SLEEP_TCS 2>,
+ <WAKE_TCS 2>,
+ <CONTROL_TCS 0>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,hawi-rpmh-clk";
+ #clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,hawi-rpmhpd";
+
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ #power-domain-cells = <1>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp-16 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_low_svs_d3_0: opp-49 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3_0>;
+ };
+
+ rpmhpd_opp_low_svs_d3: opp-50 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
+ };
+
+ rpmhpd_opp_low_svs_d2_1: opp-51 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1>;
+ };
+
+ rpmhpd_opp_low_svs_d2: opp-52 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+ };
+
+ rpmhpd_opp_low_svs_d1_1: opp-54 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1>;
+ };
+
+ rpmhpd_opp_low_svs_d1_0: opp-55 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1_0>;
+ };
+
+ rpmhpd_opp_low_svs_d1: opp-56 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs_d0_0: opp-59 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0_0>;
+ };
+
+ rpmhpd_opp_low_svs_d0: opp-60 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+ };
+
+ rpmhpd_opp_low_svs: opp-64 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_l0: opp-76 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L0>;
+ };
+
+ rpmhpd_opp_low_svs_l1: opp-80 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ };
+
+ rpmhpd_opp_low_svs_l2: opp-96 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
+ };
+
+ rpmhpd_opp_svs: opp-128 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l0: opp-144 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ rpmhpd_opp_svs_l1: opp-192 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_svs_l2: opp-224 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ rpmhpd_opp_svs_l2_0: opp-225 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2_0>;
+ };
+
+ rpmhpd_opp_nom: opp-256 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp-320 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp-336 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp-384 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l0: opp-400 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L0>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp-416 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ rpmhpd_opp_turbo_l1_0: opp-417 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1_0>;
+ };
+
+ rpmhpd_opp_turbo_l1_1: opp-418 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1_1>;
+ };
+
+ rpmhpd_opp_turbo_l1_2: opp-419 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1_2>;
+ };
+
+ rpmhpd_opp_turbo_l2: opp-432 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+ };
+
+ rpmhpd_opp_turbo_l3: opp-448 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+ };
+
+ rpmhpd_opp_turbo_l3_0: opp-449 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3_0>;
+ };
+
+ rpmhpd_opp_turbo_l3_1: opp-450 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3_1>;
+ };
+
+ rpmhpd_opp_turbo_l3_2: opp-451 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3_2>;
+ };
+
+ rpmhpd_opp_turbo_l4: opp-452 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+ };
+
+ rpmhpd_opp_turbo_l5: opp-456 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
+ };
+
+ rpmhpd_opp_super_turbo_no_cpr: opp-480 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>;
+ };
+ };
+ };
+ };
+
+ efuse@221c8000 {
+ compatible = "qcom,hawi-qfprom", "qcom,qfprom";
+ reg = <0x0 0x221c8000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpu_speed_bin: gpu-speed-bin@142 {
+ reg = <0x142 0x2>;
+ bits = <3 9>;
+ };
+ };
+
+ nsp_noc: interconnect@260c0000 {
+ compatible = "qcom,hawi-nsp-noc";
+ reg = <0x0 0x260c0000 0x0 0x21280>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ remoteproc_cdsp: remoteproc@26300000 {
+ compatible = "qcom,hawi-cdsp-pas";
+ reg = <0x0 0x26300000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_ESPI 642 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_NSP>;
+ power-domain-names = "cx",
+ "mxc",
+ "nsp";
+
+ memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ qcom,remote-pid = <5>;
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,hawi-fastrpc", "qcom,kaanapali-fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "cdsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+
+ iommus = <&apps_smmu 0x0801 0x40>,
+ <&apps_smmu 0x15c1 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+
+ iommus = <&apps_smmu 0x0802 0x40>,
+ <&apps_smmu 0x15c2 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+
+ iommus = <&apps_smmu 0x0803 0x40>,
+ <&apps_smmu 0x15c3 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+
+ iommus = <&apps_smmu 0x0804 0x40>,
+ <&apps_smmu 0x15c4 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+
+ iommus = <&apps_smmu 0x0805 0x40>,
+ <&apps_smmu 0x15c5 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+
+ iommus = <&apps_smmu 0x0806 0x40>,
+ <&apps_smmu 0x15c6 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+
+ iommus = <&apps_smmu 0x0807 0x40>,
+ <&apps_smmu 0x15c7 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+
+ iommus = <&apps_smmu 0x0808 0x40>,
+ <&apps_smmu 0x15c8 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+
+ iommus = <&apps_smmu 0x0809 0x40>,
+ <&apps_smmu 0x15c9 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+
+ iommus = <&apps_smmu 0x080c 0x40>,
+ <&apps_smmu 0x15cc 0x0>;
+ dma-coherent;
+ };
+ };
+ };
+ };
+
+ pmu@31081000 {
+ compatible = "qcom,hawi-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0x0 0x31081000 0x0 0x1000>;
+
+ interrupts = <GIC_ESPI 145 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+ llcc_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <13128000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <32472000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <37320000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <40992000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <50208000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <65664000>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <76488000>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <88464000>;
+ };
+
+ opp-8 {
+ opp-peak-kBps = <101376000>;
+ };
+
+ opp-9 {
+ opp-peak-kBps = <114720000>;
+ };
+
+ opp-10 {
+ opp-peak-kBps = <127992000>;
+ };
+ };
+ };
+
+ pmu@310b7500 {
+ compatible = "qcom,hawi-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0x0 0x310b7500 0x0 0x600>;
+
+ interrupts = <GIC_ESPI 645 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <12516000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <17574000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <35586000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <39090000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <47880000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <62622000>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <73542000>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <84360000>;
+ };
+
+ opp-8 {
+ opp-peak-kBps = <96678000>;
+ };
+ };
+ };
+
+ gem_noc: interconnect@31100000 {
+ compatible = "qcom,hawi-gem-noc";
+ reg = <0x0 0x31100000 0x0 0x160200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ llclpi_noc: interconnect@31310000 {
+ compatible = "qcom,hawi-llclpi-noc";
+ reg = <0x0 0x31310000 0x0 0x17200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system-cache-controller@31800000 {
+ compatible = "qcom,hawi-llcc";
+ reg = <0x0 0x31800000 0x0 0x200000>,
+ <0x0 0x32800000 0x0 0x200000>,
+ <0x0 0x31c00000 0x0 0x200000>,
+ <0x0 0x32c00000 0x0 0x200000>,
+ <0x0 0x34800000 0x0 0x200000>,
+ <0x0 0x34c00000 0x0 0x200000>;
+ reg-names = "llcc0_base",
+ "llcc1_base",
+ "llcc2_base",
+ "llcc3_base",
+ "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
+
+ interrupts = <GIC_ESPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&cpucp_slc_mem_sub>;
+ };
+
+ sram: sram@81f08000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x81f08000 0x0 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x81f08000 0x200>;
+
+ pdp_rx: scp-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ pdp_tx: scp-sram-section@80 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x80 0x80>;
+ };
+ };
+ };
+
+ thermal-zones {
+ camera-0-thermal {
+ thermal-sensors = <&tsens6 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ camera-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-1-thermal {
+ thermal-sensors = <&tsens6 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ camera-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-thermal {
+ thermal-sensors = <&tsens2 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-0-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-thermal {
+ thermal-sensors = <&tsens2 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-0-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-thermal {
+ thermal-sensors = <&tsens2 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-0-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-thermal {
+ thermal-sensors = <&tsens2 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-1-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-thermal {
+ thermal-sensors = <&tsens2 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-1-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-2-thermal {
+ thermal-sensors = <&tsens2 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-1-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-0-thermal {
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-2-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-1-thermal {
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-2-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-3-0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-3-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-3-1-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-3-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-4-0-thermal {
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-4-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-4-1-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-4-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-5-0-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-5-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-5-1-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-5-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-6-0-thermal {
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-6-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-6-1-thermal {
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-6-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-7-0-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-7-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-7-1-thermal {
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu-7-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-0-thermal {
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpullc-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-1-thermal {
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpullc-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-thermal {
+ thermal-sensors = <&tsens6 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ ddr-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-0-0-thermal {
+ thermal-sensors = <&tsens5 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-0-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-0-1-thermal {
+ thermal-sensors = <&tsens5 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-0-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-0-2-thermal {
+ thermal-sensors = <&tsens5 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-0-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-1-0-thermal {
+ thermal-sensors = <&tsens5 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpu-1-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-1-1-thermal {
+ thermal-sensors = <&tsens5 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpu-1-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-1-2-thermal {
+ thermal-sensors = <&tsens5 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpu-1-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-2-0-thermal {
+ thermal-sensors = <&tsens5 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpu-2-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-2-1-thermal {
+ thermal-sensors = <&tsens5 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpu-2-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-2-2-thermal {
+ thermal-sensors = <&tsens5 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpu-2-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-0-thermal {
+ thermal-sensors = <&tsens5 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-1-thermal {
+ thermal-sensors = <&tsens5 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss-0-thermal {
+ thermal-sensors = <&tsens6 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss-1-thermal {
+ thermal-sensors = <&tsens6 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss-2-thermal {
+ thermal-sensors = <&tsens6 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss-3-thermal {
+ thermal-sensors = <&tsens6 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss-3-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspllv-0-0-thermal {
+ thermal-sensors = <&tsens3 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspllv-0-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspllv-0-1-thermal {
+ thermal-sensors = <&tsens3 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspllv-0-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspllv-1-0-thermal {
+ thermal-sensors = <&tsens3 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspllv-1-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspllv-1-1-thermal {
+ thermal-sensors = <&tsens3 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspllv-1-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspmxu0-0-0-thermal {
+ thermal-sensors = <&tsens4 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspmxu0-0-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspmxu0-0-1-thermal {
+ thermal-sensors = <&tsens4 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspmxu0-0-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspmxu0-1-0-thermal {
+ thermal-sensors = <&tsens4 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspmxu0-1-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspmxu0-1-1-thermal {
+ thermal-sensors = <&tsens4 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspmxu0-1-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspmxu1-0-0-thermal {
+ thermal-sensors = <&tsens4 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspmxu1-0-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspmxu1-0-1-thermal {
+ thermal-sensors = <&tsens4 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspmxu1-0-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspmxu1-1-0-thermal {
+ thermal-sensors = <&tsens4 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspmxu1-1-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspmxu1-1-1-thermal {
+ thermal-sensors = <&tsens4 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspmxu1-1-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspmxutop-thermal {
+ thermal-sensors = <&tsens4 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspmxutop-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspq6-thermal {
+ thermal-sensors = <&tsens3 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspq6-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspvxu-0-thermal {
+ thermal-sensors = <&tsens3 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspvxu-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspvxu-1-thermal {
+ thermal-sensors = <&tsens3 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspvxu-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspvxu-2-thermal {
+ thermal-sensors = <&tsens3 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspvxu-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspvxu-3-thermal {
+ thermal-sensors = <&tsens3 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nspvxu-3-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-0-thermal {
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-thermal {
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-2-thermal {
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-3-thermal {
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-3-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-4-thermal {
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-4-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ thermal-sensors = <&tsens6 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ video-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--
2.55.0
^ permalink raw reply [flat|nested] 10+ messages in thread