From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: Jonathan Cameron <jic23@kernel.org>
Cc: dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org,
robh@kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org,
linux-iio@vger.kernel.org, s32@nxp.com,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
chester62515@gmail.com, mbrugger@suse.com,
ghennadi.procopciuc@oss.nxp.com
Subject: Re: [PATCH v2 2/2] iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms
Date: Thu, 11 Sep 2025 14:55:00 +0200 [thread overview]
Message-ID: <b4d2ad54-54d5-4c26-be49-b6ac671683d2@linaro.org> (raw)
In-Reply-To: <20250910183212.6640e662@jic23-huawei>
Hi Jonathan,
thanks for the review
On 10/09/2025 19:32, Jonathan Cameron wrote:
> On Wed, 10 Sep 2025 17:57:56 +0200
> Daniel Lezcano <daniel.lezcano@linaro.org> wrote:
[ ... ]
>> +/* Main Configuration Register */
>> +#define REG_ADC_MCR(__base) ((__base) + 0x00)
>
> I'm not really convinced these macros help over just having
> readl(info->regs + NXP_SADC_MCR_REG);
That is really a matter of taste :)
I used to create this format in order to stick the macros with the
debugfs register code which is not part of these changes. There is a
similar format in drivers/clocksource/timer-nxp-stm.c or
driver/thermal/mediatek/lvts.c IMHO is less prone to error than base +
REG all around the code.
Do you want me to convert all the macros to info->__base + MACRO ?
[ ... ]
>> +static const struct iio_chan_spec nxp_sar_adc_iio_channels[] = {
>> + ADC_CHAN(0, IIO_VOLTAGE),
>> + ADC_CHAN(1, IIO_VOLTAGE),
>> + ADC_CHAN(2, IIO_VOLTAGE),
>> + ADC_CHAN(3, IIO_VOLTAGE),
>> + ADC_CHAN(4, IIO_VOLTAGE),
>> + ADC_CHAN(5, IIO_VOLTAGE),
>> + ADC_CHAN(6, IIO_VOLTAGE),
>> + ADC_CHAN(7, IIO_VOLTAGE),
>> + IIO_CHAN_SOFT_TIMESTAMP(32),
>
> Whilst we only insist on monotonic numbering, putting it all the way down
> at 32 seems excessive. Why not 8? Perhaps a comment if this is to avoid
> moving it for some future feature.
The ADC has 8 channels for external acquisition however others channels
8->31 are described as reserved. They may evolve in the future to more
channels. That is probably the reason why 32 is used here.
[ ... ]
>> + indio_dev->name = dev_name(dev);
>
> This should be the 'part number'. That is a little ill defined
> for a SoC integrated ADC, but generally not what we get from dev_name()
> on the platform_device.
Sorry, I don't get the comment. If I refer to the different drivers
there is not consistency with the iio_dev->name.
rtq6056.c: indio_dev->name = "rtq6056";
rzg2l_adc.c: indio_dev->name = DRIVER_NAME;
sc27xx_adc.c: indio_dev->name = dev_name(dev);
mt6359-auxadc.c: indio_dev->name = adc_dev->chip_info->model_name;
mcp3911.c: indio_dev->name = spi_get_device_id(spi)->name;
Are you suggesting to use the compatible part number ?
indio->name = "s32g2-sar-adc";
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next prev parent reply other threads:[~2025-09-11 12:55 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-10 15:57 [PATCH v2 0/2] NXP SAR ADC IIO driver for " Daniel Lezcano
2025-09-10 15:57 ` [PATCH v2 1/2] dt-bindings: iio: adc: Add the NXP SAR ADC " Daniel Lezcano
2025-09-10 15:57 ` [PATCH v2 2/2] iio: adc: Add the NXP SAR ADC support for the " Daniel Lezcano
2025-09-10 17:32 ` Jonathan Cameron
2025-09-11 12:55 ` Daniel Lezcano [this message]
2025-09-11 13:26 ` David Lechner
2025-09-12 14:17 ` Jonathan Cameron
2025-09-12 15:10 ` Nuno Sá
2025-09-12 14:18 ` Jonathan Cameron
2025-09-11 20:10 ` David Lechner
2025-09-11 23:03 ` Daniel Lezcano
2025-09-12 5:38 ` Andy Shevchenko
2025-09-12 8:19 ` Nuno Sá
2025-09-12 14:21 ` Jonathan Cameron
2025-09-12 6:00 ` Andy Shevchenko
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