* [PATCH v3] PCI: dwc: Add PCIe event counters for groups 5 to 7 in DWC debugfs
@ 2026-03-07 2:01 Hans Zhang
2026-03-07 2:03 ` Hans Zhang
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Hans Zhang @ 2026-03-07 2:01 UTC (permalink / raw)
To: lpieralisi, jingoohan1, mani, kwilczynski, bhelgaas
Cc: robh, linux-pci, linux-kernel, Hans Zhang, Cheng Xin
Extend the DesignWare PCIe controller's debugfs statistical counter
interface with event definitions from groups 5 through 7 as documented
in the DWC PCIe Databook (version 6.30a, section 3.8.2.3, Tables 3-59,
3-60, 3-61). These counters provide visibility into Layer1 non-error
events (link state transitions,ASPM, L1 substates), Layer2 DLLP
exchanges, and Layer3 TLP transactions.
The counters are exposed under the debugfs statistical counter directory,
allowing users to monitor link behavior and diagnose PCIe protocol issues
more effectively.
Co-developed-by: Cheng Xin <chengqin195275@126.com>
Signed-off-by: Cheng Xin <chengqin195275@126.com>
Signed-off-by: Hans Zhang <18255117159@163.com>
---
Thank you, Cheng Xin, for providing the 6.30a version of the DWC PCIe Data Book.
Changes for v3:
- Correct the incorrect version information of the databook. Thank you, Shawn, for the reminder.
Changes for v2:
- Sorry, I sent the patch multiple times in a row. The first version of
the email was incorrect. The email address of Cheng Xin has been corrected.
---
.../controller/dwc/pcie-designware-debugfs.c | 52 ++++++++++++++++++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
index 0d1340c9b364..2efddb21b2b2 100644
--- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c
+++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
@@ -131,13 +131,16 @@ static const u32 err_inj_type_mask[] = {
* supported in DWC RAS DES
* @name: Name of the error counter
* @group_no: Group number that the event belongs to. The value can range
- * from 0 to 4
+ * from 0 to 7
* @event_no: Event number of the particular event. The value ranges are:
* Group 0: 0 - 10
* Group 1: 5 - 13
* Group 2: 0 - 7
* Group 3: 0 - 5
* Group 4: 0 - 1
+ * Group 5: 0 - 13
+ * Group 6: 0 - 6
+ * Group 7: 0 - 25
*/
struct dwc_pcie_event_counter {
const char *name;
@@ -181,6 +184,53 @@ static const struct dwc_pcie_event_counter event_list[] = {
{"completion_timeout", 0x3, 0x5},
{"ebuf_skp_add", 0x4, 0x0},
{"ebuf_skp_del", 0x4, 0x1},
+ {"l0_to_recovery_entry", 0x5, 0x0},
+ {"l1_to_recovery_entry", 0x5, 0x1},
+ {"tx_l0s_entry", 0x5, 0x2},
+ {"rx_l0s_entry", 0x5, 0x3},
+ {"aspm_l1_reject", 0x5, 0x4},
+ {"l1_entry", 0x5, 0x5},
+ {"l1_cpm", 0x5, 0x6},
+ {"l1.1_entry", 0x5, 0x7},
+ {"l1.2_entry", 0x5, 0x8},
+ {"l1_short_duration", 0x5, 0x9},
+ {"l1.2_abort", 0x5, 0xa},
+ {"l2_entry", 0x5, 0xb},
+ {"speed_change", 0x5, 0xc},
+ {"link_width_change", 0x5, 0xd},
+ {"tx_ack_dllp", 0x6, 0x0},
+ {"tx_update_fc_dllp", 0x6, 0x1},
+ {"rx_ack_dllp", 0x6, 0x2},
+ {"rx_update_fc_dllp", 0x6, 0x3},
+ {"rx_nullified_tlp", 0x6, 0x4},
+ {"tx_nullified_tlp", 0x6, 0x5},
+ {"rx_duplicate_tlp", 0x6, 0x6},
+ {"tx_memory_write", 0x7, 0x0},
+ {"tx_memory_read", 0x7, 0x1},
+ {"tx_configuration_write", 0x7, 0x2},
+ {"tx_configuration_read", 0x7, 0x3},
+ {"tx_io_write", 0x7, 0x4},
+ {"tx_io_read", 0x7, 0x5},
+ {"tx_completion_without_data", 0x7, 0x6},
+ {"tx_completion_w_data", 0x7, 0x7},
+ {"tx_message_tlp_pcie_vc_only", 0x7, 0x8},
+ {"tx_atomic", 0x7, 0x9},
+ {"tx_tlp_with_prefix", 0x7, 0xa},
+ {"rx_memory_write", 0x7, 0xb},
+ {"rx_memory_read", 0x7, 0xc},
+ {"rx_configuration_write", 0x7, 0xd},
+ {"rx_configuration_read", 0x7, 0xe},
+ {"rx_io_write", 0x7, 0xf},
+ {"rx_io_read", 0x7, 0x10},
+ {"rx_completion_without_data", 0x7, 0x11},
+ {"rx_completion_w_data", 0x7, 0x12},
+ {"rx_message_tlp_pcie_vc_only", 0x7, 0x13},
+ {"rx_atomic", 0x7, 0x14},
+ {"rx_tlp_with_prefix", 0x7, 0x15},
+ {"tx_ccix_tlp", 0x7, 0x16},
+ {"rx_ccix_tlp", 0x7, 0x17},
+ {"tx_deferrable_memory_write_tlp", 0x7, 0x18},
+ {"rx_deferrable_memory_write_tlp", 0x7, 0x19},
};
static ssize_t lane_detect_read(struct file *file, char __user *buf,
base-commit: 325a118c12045239076b7ea9e66391dd6f56f72e
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v3] PCI: dwc: Add PCIe event counters for groups 5 to 7 in DWC debugfs
2026-03-07 2:01 [PATCH v3] PCI: dwc: Add PCIe event counters for groups 5 to 7 in DWC debugfs Hans Zhang
@ 2026-03-07 2:03 ` Hans Zhang
2026-03-07 3:23 ` Shawn Lin
2026-03-26 17:23 ` Manivannan Sadhasivam
2 siblings, 0 replies; 4+ messages in thread
From: Hans Zhang @ 2026-03-07 2:03 UTC (permalink / raw)
To: lpieralisi, jingoohan1, mani, kwilczynski, bhelgaas, Shawn Lin
Cc: robh, linux-pci, linux-kernel, Cheng Xin
[+cc Shawn]
On 3/7/26 10:01, Hans Zhang wrote:
> Extend the DesignWare PCIe controller's debugfs statistical counter
> interface with event definitions from groups 5 through 7 as documented
> in the DWC PCIe Databook (version 6.30a, section 3.8.2.3, Tables 3-59,
> 3-60, 3-61). These counters provide visibility into Layer1 non-error
> events (link state transitions,ASPM, L1 substates), Layer2 DLLP
> exchanges, and Layer3 TLP transactions.
>
> The counters are exposed under the debugfs statistical counter directory,
> allowing users to monitor link behavior and diagnose PCIe protocol issues
> more effectively.
>
> Co-developed-by: Cheng Xin <chengqin195275@126.com>
> Signed-off-by: Cheng Xin <chengqin195275@126.com>
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
> Thank you, Cheng Xin, for providing the 6.30a version of the DWC PCIe Data Book.
>
> Changes for v3:
> - Correct the incorrect version information of the databook. Thank you, Shawn, for the reminder.
>
> Changes for v2:
> - Sorry, I sent the patch multiple times in a row. The first version of
> the email was incorrect. The email address of Cheng Xin has been corrected.
> ---
> .../controller/dwc/pcie-designware-debugfs.c | 52 ++++++++++++++++++-
> 1 file changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
> index 0d1340c9b364..2efddb21b2b2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
> @@ -131,13 +131,16 @@ static const u32 err_inj_type_mask[] = {
> * supported in DWC RAS DES
> * @name: Name of the error counter
> * @group_no: Group number that the event belongs to. The value can range
> - * from 0 to 4
> + * from 0 to 7
> * @event_no: Event number of the particular event. The value ranges are:
> * Group 0: 0 - 10
> * Group 1: 5 - 13
> * Group 2: 0 - 7
> * Group 3: 0 - 5
> * Group 4: 0 - 1
> + * Group 5: 0 - 13
> + * Group 6: 0 - 6
> + * Group 7: 0 - 25
> */
> struct dwc_pcie_event_counter {
> const char *name;
> @@ -181,6 +184,53 @@ static const struct dwc_pcie_event_counter event_list[] = {
> {"completion_timeout", 0x3, 0x5},
> {"ebuf_skp_add", 0x4, 0x0},
> {"ebuf_skp_del", 0x4, 0x1},
> + {"l0_to_recovery_entry", 0x5, 0x0},
> + {"l1_to_recovery_entry", 0x5, 0x1},
> + {"tx_l0s_entry", 0x5, 0x2},
> + {"rx_l0s_entry", 0x5, 0x3},
> + {"aspm_l1_reject", 0x5, 0x4},
> + {"l1_entry", 0x5, 0x5},
> + {"l1_cpm", 0x5, 0x6},
> + {"l1.1_entry", 0x5, 0x7},
> + {"l1.2_entry", 0x5, 0x8},
> + {"l1_short_duration", 0x5, 0x9},
> + {"l1.2_abort", 0x5, 0xa},
> + {"l2_entry", 0x5, 0xb},
> + {"speed_change", 0x5, 0xc},
> + {"link_width_change", 0x5, 0xd},
> + {"tx_ack_dllp", 0x6, 0x0},
> + {"tx_update_fc_dllp", 0x6, 0x1},
> + {"rx_ack_dllp", 0x6, 0x2},
> + {"rx_update_fc_dllp", 0x6, 0x3},
> + {"rx_nullified_tlp", 0x6, 0x4},
> + {"tx_nullified_tlp", 0x6, 0x5},
> + {"rx_duplicate_tlp", 0x6, 0x6},
> + {"tx_memory_write", 0x7, 0x0},
> + {"tx_memory_read", 0x7, 0x1},
> + {"tx_configuration_write", 0x7, 0x2},
> + {"tx_configuration_read", 0x7, 0x3},
> + {"tx_io_write", 0x7, 0x4},
> + {"tx_io_read", 0x7, 0x5},
> + {"tx_completion_without_data", 0x7, 0x6},
> + {"tx_completion_w_data", 0x7, 0x7},
> + {"tx_message_tlp_pcie_vc_only", 0x7, 0x8},
> + {"tx_atomic", 0x7, 0x9},
> + {"tx_tlp_with_prefix", 0x7, 0xa},
> + {"rx_memory_write", 0x7, 0xb},
> + {"rx_memory_read", 0x7, 0xc},
> + {"rx_configuration_write", 0x7, 0xd},
> + {"rx_configuration_read", 0x7, 0xe},
> + {"rx_io_write", 0x7, 0xf},
> + {"rx_io_read", 0x7, 0x10},
> + {"rx_completion_without_data", 0x7, 0x11},
> + {"rx_completion_w_data", 0x7, 0x12},
> + {"rx_message_tlp_pcie_vc_only", 0x7, 0x13},
> + {"rx_atomic", 0x7, 0x14},
> + {"rx_tlp_with_prefix", 0x7, 0x15},
> + {"tx_ccix_tlp", 0x7, 0x16},
> + {"rx_ccix_tlp", 0x7, 0x17},
> + {"tx_deferrable_memory_write_tlp", 0x7, 0x18},
> + {"rx_deferrable_memory_write_tlp", 0x7, 0x19},
> };
>
> static ssize_t lane_detect_read(struct file *file, char __user *buf,
>
> base-commit: 325a118c12045239076b7ea9e66391dd6f56f72e
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v3] PCI: dwc: Add PCIe event counters for groups 5 to 7 in DWC debugfs
2026-03-07 2:01 [PATCH v3] PCI: dwc: Add PCIe event counters for groups 5 to 7 in DWC debugfs Hans Zhang
2026-03-07 2:03 ` Hans Zhang
@ 2026-03-07 3:23 ` Shawn Lin
2026-03-26 17:23 ` Manivannan Sadhasivam
2 siblings, 0 replies; 4+ messages in thread
From: Shawn Lin @ 2026-03-07 3:23 UTC (permalink / raw)
To: Hans Zhang
Cc: shawn.lin, robh, linux-pci, linux-kernel, Cheng Xin, lpieralisi,
jingoohan1, mani, kwilczynski, bhelgaas
在 2026/03/07 星期六 10:01, Hans Zhang 写道:
> Extend the DesignWare PCIe controller's debugfs statistical counter
> interface with event definitions from groups 5 through 7 as documented
> in the DWC PCIe Databook (version 6.30a, section 3.8.2.3, Tables 3-59,
> 3-60, 3-61). These counters provide visibility into Layer1 non-error
> events (link state transitions,ASPM, L1 substates), Layer2 DLLP
> exchanges, and Layer3 TLP transactions.
>
Re-check the events one by one against the v6.30a databook, the new
events are correct.
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> The counters are exposed under the debugfs statistical counter directory,
> allowing users to monitor link behavior and diagnose PCIe protocol issues
> more effectively.
>
> Co-developed-by: Cheng Xin <chengqin195275@126.com>
> Signed-off-by: Cheng Xin <chengqin195275@126.com>
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
> Thank you, Cheng Xin, for providing the 6.30a version of the DWC PCIe Data Book.
>
> Changes for v3:
> - Correct the incorrect version information of the databook. Thank you, Shawn, for the reminder.
>
> Changes for v2:
> - Sorry, I sent the patch multiple times in a row. The first version of
> the email was incorrect. The email address of Cheng Xin has been corrected.
> ---
> .../controller/dwc/pcie-designware-debugfs.c | 52 ++++++++++++++++++-
> 1 file changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
> index 0d1340c9b364..2efddb21b2b2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
> @@ -131,13 +131,16 @@ static const u32 err_inj_type_mask[] = {
> * supported in DWC RAS DES
> * @name: Name of the error counter
> * @group_no: Group number that the event belongs to. The value can range
> - * from 0 to 4
> + * from 0 to 7
> * @event_no: Event number of the particular event. The value ranges are:
> * Group 0: 0 - 10
> * Group 1: 5 - 13
> * Group 2: 0 - 7
> * Group 3: 0 - 5
> * Group 4: 0 - 1
> + * Group 5: 0 - 13
> + * Group 6: 0 - 6
> + * Group 7: 0 - 25
> */
> struct dwc_pcie_event_counter {
> const char *name;
> @@ -181,6 +184,53 @@ static const struct dwc_pcie_event_counter event_list[] = {
> {"completion_timeout", 0x3, 0x5},
> {"ebuf_skp_add", 0x4, 0x0},
> {"ebuf_skp_del", 0x4, 0x1},
> + {"l0_to_recovery_entry", 0x5, 0x0},
> + {"l1_to_recovery_entry", 0x5, 0x1},
> + {"tx_l0s_entry", 0x5, 0x2},
> + {"rx_l0s_entry", 0x5, 0x3},
> + {"aspm_l1_reject", 0x5, 0x4},
> + {"l1_entry", 0x5, 0x5},
> + {"l1_cpm", 0x5, 0x6},
> + {"l1.1_entry", 0x5, 0x7},
> + {"l1.2_entry", 0x5, 0x8},
> + {"l1_short_duration", 0x5, 0x9},
> + {"l1.2_abort", 0x5, 0xa},
> + {"l2_entry", 0x5, 0xb},
> + {"speed_change", 0x5, 0xc},
> + {"link_width_change", 0x5, 0xd},
> + {"tx_ack_dllp", 0x6, 0x0},
> + {"tx_update_fc_dllp", 0x6, 0x1},
> + {"rx_ack_dllp", 0x6, 0x2},
> + {"rx_update_fc_dllp", 0x6, 0x3},
> + {"rx_nullified_tlp", 0x6, 0x4},
> + {"tx_nullified_tlp", 0x6, 0x5},
> + {"rx_duplicate_tlp", 0x6, 0x6},
> + {"tx_memory_write", 0x7, 0x0},
> + {"tx_memory_read", 0x7, 0x1},
> + {"tx_configuration_write", 0x7, 0x2},
> + {"tx_configuration_read", 0x7, 0x3},
> + {"tx_io_write", 0x7, 0x4},
> + {"tx_io_read", 0x7, 0x5},
> + {"tx_completion_without_data", 0x7, 0x6},
> + {"tx_completion_w_data", 0x7, 0x7},
> + {"tx_message_tlp_pcie_vc_only", 0x7, 0x8},
> + {"tx_atomic", 0x7, 0x9},
> + {"tx_tlp_with_prefix", 0x7, 0xa},
> + {"rx_memory_write", 0x7, 0xb},
> + {"rx_memory_read", 0x7, 0xc},
> + {"rx_configuration_write", 0x7, 0xd},
> + {"rx_configuration_read", 0x7, 0xe},
> + {"rx_io_write", 0x7, 0xf},
> + {"rx_io_read", 0x7, 0x10},
> + {"rx_completion_without_data", 0x7, 0x11},
> + {"rx_completion_w_data", 0x7, 0x12},
> + {"rx_message_tlp_pcie_vc_only", 0x7, 0x13},
> + {"rx_atomic", 0x7, 0x14},
> + {"rx_tlp_with_prefix", 0x7, 0x15},
> + {"tx_ccix_tlp", 0x7, 0x16},
> + {"rx_ccix_tlp", 0x7, 0x17},
> + {"tx_deferrable_memory_write_tlp", 0x7, 0x18},
> + {"rx_deferrable_memory_write_tlp", 0x7, 0x19},
> };
>
> static ssize_t lane_detect_read(struct file *file, char __user *buf,
>
> base-commit: 325a118c12045239076b7ea9e66391dd6f56f72e
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v3] PCI: dwc: Add PCIe event counters for groups 5 to 7 in DWC debugfs
2026-03-07 2:01 [PATCH v3] PCI: dwc: Add PCIe event counters for groups 5 to 7 in DWC debugfs Hans Zhang
2026-03-07 2:03 ` Hans Zhang
2026-03-07 3:23 ` Shawn Lin
@ 2026-03-26 17:23 ` Manivannan Sadhasivam
2 siblings, 0 replies; 4+ messages in thread
From: Manivannan Sadhasivam @ 2026-03-26 17:23 UTC (permalink / raw)
To: lpieralisi, jingoohan1, kwilczynski, bhelgaas, Hans Zhang
Cc: robh, linux-pci, linux-kernel, Cheng Xin
On Sat, 07 Mar 2026 10:01:52 +0800, Hans Zhang wrote:
> Extend the DesignWare PCIe controller's debugfs statistical counter
> interface with event definitions from groups 5 through 7 as documented
> in the DWC PCIe Databook (version 6.30a, section 3.8.2.3, Tables 3-59,
> 3-60, 3-61). These counters provide visibility into Layer1 non-error
> events (link state transitions,ASPM, L1 substates), Layer2 DLLP
> exchanges, and Layer3 TLP transactions.
>
> [...]
Applied, thanks!
[1/1] PCI: dwc: Add PCIe event counters for groups 5 to 7 in DWC debugfs
commit: 698dab284b9d1c8aace73af8aaf0cfb74fc8ce92
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
^ permalink raw reply [flat|nested] 4+ messages in thread
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