Re: [PATCH v8 3/4] i2c: tegra: Add logic to support different register offsets

[Jon Hunter <jonathanh@nvidia.com>]

On 20/01/2026 09:20, Kartik Rajput wrote:
> Tegra410 use different offsets for existing I2C registers, update
> the logic to use appropriate offsets per SoC.
> 
> As the registers offsets are now also defined for dvc and vi, following

So this is still not accurate because the DVC offsets definition have 
not changed.

> -static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
> -		       unsigned int reg)
> -{
> -	writel_relaxed(val, i2c_dev->base + reg);
> -}
> -
> -static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
> -{
> -	return readl_relaxed(i2c_dev->base + reg);
> -}

...

> @@ -619,14 +712,14 @@ static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
>   {
>   	u32 val;
>   
> -	val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
> +	val = i2c_readl(i2c_dev, DVC_CTRL_REG3);
>   	val |= DVC_CTRL_REG3_SW_PROG;
>   	val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
> -	dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
> +	writel_relaxed(val, i2c_dev->base + DVC_CTRL_REG3);
>   
> -	val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
> +	val = i2c_readl(i2c_dev, DVC_CTRL_REG1);
>   	val |= DVC_CTRL_REG1_INTR_EN;
> -	dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
> +	writel_relaxed(val, i2c_dev->base + DVC_CTRL_REG1);
>   }

Looking at the above, I think I would be tempted to leave this as-is and 
not make any changes here to reduce the diff.

Jon

-- 
nvpublic