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* [PATCH v1] mmc: sdhci-of-dwcmshc: fix init for AXI clock
@ 2026-01-14 12:21 hehuan1
  2026-01-21  6:33 ` Adrian Hunter
  2026-01-22 18:03 ` Ulf Hansson
  0 siblings, 2 replies; 3+ messages in thread
From: hehuan1 @ 2026-01-14 12:21 UTC (permalink / raw)
  To: adrian.hunter, ulf.hansson, linux-mmc, linux-kernel
  Cc: ningyu, linmin, pinkesh.vaghela, xuxiang, hehuan1

From: Huan He <hehuan1@eswincomputing.com>

Accessing the High-Speed registers requires the AXI clock to be enabled.

Signed-off-by: Huan He <hehuan1@eswincomputing.com>
---
 drivers/mmc/host/sdhci-of-dwcmshc.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 51949cde0958..d795745987e3 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -1588,6 +1588,7 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
 {
 	u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
 	unsigned int val, hsp_int_status, hsp_pwr_ctrl;
+	static const char * const clk_ids[] = {"axi"};
 	struct of_phandle_args args;
 	struct eic7700_priv *priv;
 	struct regmap *hsp_regmap;
@@ -1605,6 +1606,11 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
 		return ret;
 	}
 
+	ret = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
+					    ARRAY_SIZE(clk_ids), clk_ids);
+	if (ret)
+		return ret;
+
 	ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args);
 	if (ret) {
 		dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret);
-- 
2.25.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v1] mmc: sdhci-of-dwcmshc: fix init for AXI clock
  2026-01-14 12:21 [PATCH v1] mmc: sdhci-of-dwcmshc: fix init for AXI clock hehuan1
@ 2026-01-21  6:33 ` Adrian Hunter
  2026-01-22 18:03 ` Ulf Hansson
  1 sibling, 0 replies; 3+ messages in thread
From: Adrian Hunter @ 2026-01-21  6:33 UTC (permalink / raw)
  To: hehuan1, ulf.hansson, linux-mmc, linux-kernel
  Cc: ningyu, linmin, pinkesh.vaghela, xuxiang

On 14/01/2026 14:21, hehuan1@eswincomputing.com wrote:
> From: Huan He <hehuan1@eswincomputing.com>
> 
> Accessing the High-Speed registers requires the AXI clock to be enabled.
> 
> Signed-off-by: Huan He <hehuan1@eswincomputing.com>

Fixes tag?

Nevertheless:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-of-dwcmshc.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index 51949cde0958..d795745987e3 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -1588,6 +1588,7 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
>  {
>  	u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
>  	unsigned int val, hsp_int_status, hsp_pwr_ctrl;
> +	static const char * const clk_ids[] = {"axi"};
>  	struct of_phandle_args args;
>  	struct eic7700_priv *priv;
>  	struct regmap *hsp_regmap;
> @@ -1605,6 +1606,11 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
>  		return ret;
>  	}
>  
> +	ret = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
> +					    ARRAY_SIZE(clk_ids), clk_ids);
> +	if (ret)
> +		return ret;
> +
>  	ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args);
>  	if (ret) {
>  		dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret);


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v1] mmc: sdhci-of-dwcmshc: fix init for AXI clock
  2026-01-14 12:21 [PATCH v1] mmc: sdhci-of-dwcmshc: fix init for AXI clock hehuan1
  2026-01-21  6:33 ` Adrian Hunter
@ 2026-01-22 18:03 ` Ulf Hansson
  1 sibling, 0 replies; 3+ messages in thread
From: Ulf Hansson @ 2026-01-22 18:03 UTC (permalink / raw)
  To: hehuan1
  Cc: adrian.hunter, linux-mmc, linux-kernel, ningyu, linmin,
	pinkesh.vaghela, xuxiang

On Wed, 14 Jan 2026 at 13:21, <hehuan1@eswincomputing.com> wrote:
>
> From: Huan He <hehuan1@eswincomputing.com>
>
> Accessing the High-Speed registers requires the AXI clock to be enabled.
>
> Signed-off-by: Huan He <hehuan1@eswincomputing.com>

Applied for fixes and by adding a fixes tag, thanks!

Kind regards
Uffe


> ---
>  drivers/mmc/host/sdhci-of-dwcmshc.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index 51949cde0958..d795745987e3 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -1588,6 +1588,7 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
>  {
>         u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
>         unsigned int val, hsp_int_status, hsp_pwr_ctrl;
> +       static const char * const clk_ids[] = {"axi"};
>         struct of_phandle_args args;
>         struct eic7700_priv *priv;
>         struct regmap *hsp_regmap;
> @@ -1605,6 +1606,11 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
>                 return ret;
>         }
>
> +       ret = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
> +                                           ARRAY_SIZE(clk_ids), clk_ids);
> +       if (ret)
> +               return ret;
> +
>         ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args);
>         if (ret) {
>                 dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret);
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2026-01-22 18:03 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-01-14 12:21 [PATCH v1] mmc: sdhci-of-dwcmshc: fix init for AXI clock hehuan1
2026-01-21  6:33 ` Adrian Hunter
2026-01-22 18:03 ` Ulf Hansson

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