[PATCH 0/3] clk: socfpga: convert clock managers to CLK_OF_DECLARE()

[PATCH 0/3] clk: socfpga: convert clock managers to CLK_OF_DECLARE()

[adrian.ho.yin.ng]

From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

The SoCFPGA Stratix10, Agilex, and Agilex5 clock managers are currently
registered as platform drivers via core_initcall(). That is too late for
early OF clock consumers: TIMER_OF_DECLARE callbacks run from time_init()
before those drivers probe, and the DW APB timer cannot defer, so
clk_get() fails and the timer is never brought up.

As discussed on the list [1], convert these drivers to CLK_OF_DECLARE()
so the providers are registered from of_clk_init() and clocks are
available before platform devices probe.

This series applies the same conversion to Agilex (including eASIC N5X),
Agilex5, and Stratix10.

Boot-tested on Agilex7 (agilex7dksiagf014eb): dw_apb_timer registers as
clocksource early, with no clk_get() failures.

[1] https://lore.kernel.org/all/20260903175356.BF1461F000E9@smtp.kernel.org/

Adrian Ng Ho Yin (3):
  clk: socfpga: agilex: convert to CLK_OF_DECLARE()
  clk: socfpga: agilex5: convert to CLK_OF_DECLARE()
  clk: socfpga: stratix10: convert to CLK_OF_DECLARE()

 drivers/clk/socfpga/clk-agilex.c  | 83 +++++++++++--------------------
 drivers/clk/socfpga/clk-agilex5.c | 56 +++++---------------
 drivers/clk/socfpga/clk-s10.c     | 50 +++++--------------
 3 files changed, 56 insertions(+), 133 deletions(-)

-- 
2.49.GIT

[PATCH 1/3] clk: socfpga: agilex: convert to CLK_OF_DECLARE()

[adrian.ho.yin.ng]

From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Register Agilex and eASIC N5X clocks at of_clk_init() so they are
available before platform devices probe.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 drivers/clk/socfpga/clk-agilex.c | 83 +++++++++++---------------------
 1 file changed, 28 insertions(+), 55 deletions(-)

diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 2bdea1997b5e..64a20c727d16 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -4,8 +4,9 @@
  */
 #include <linux/slab.h>
 #include <linux/clk-provider.h>
+#include <linux/io.h>
 #include <linux/of.h>
-#include <linux/platform_device.h>
+#include <linux/of_address.h>
 
 #include <dt-bindings/clock/agilex-clock.h>
 
@@ -454,24 +455,26 @@ static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks,
 	return 0;
 }
 
-static int agilex_clkmgr_init(struct platform_device *pdev)
+static void __init agilex_clkmgr_init(struct device_node *np)
 {
-	struct device_node *np = pdev->dev.of_node;
-	struct device *dev = &pdev->dev;
 	struct stratix10_clock_data *clk_data;
 	void __iomem *base;
 	int i, num_clks;
 
-	base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
+	base = of_iomap(np, 0);
+	if (!base) {
+		pr_err("%s: failed to map clock registers\n", __func__);
+		return;
+	}
 
 	num_clks = AGILEX_NUM_CLKS;
 
-	clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
-				num_clks), GFP_KERNEL);
-	if (!clk_data)
-		return -ENOMEM;
+	clk_data = kzalloc(struct_size(clk_data, clk_data.hws, num_clks),
+			   GFP_KERNEL);
+	if (!clk_data) {
+		iounmap(base);
+		return;
+	}
 
 	clk_data->clk_data.num = num_clks;
 	clk_data->base = base;
@@ -491,27 +494,28 @@ static int agilex_clkmgr_init(struct platform_device *pdev)
 	agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
 			      clk_data);
 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
-	return 0;
 }
 
-static int n5x_clkmgr_init(struct platform_device *pdev)
+static void __init n5x_clkmgr_init(struct device_node *np)
 {
-	struct device_node *np = pdev->dev.of_node;
-	struct device *dev = &pdev->dev;
 	struct stratix10_clock_data *clk_data;
 	void __iomem *base;
 	int i, num_clks;
 
-	base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
+	base = of_iomap(np, 0);
+	if (!base) {
+		pr_err("%s: failed to map clock registers\n", __func__);
+		return;
+	}
 
 	num_clks = AGILEX_NUM_CLKS;
 
-	clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
-				num_clks), GFP_KERNEL);
-	if (!clk_data)
-		return -ENOMEM;
+	clk_data = kzalloc(struct_size(clk_data, clk_data.hws, num_clks),
+			   GFP_KERNEL);
+	if (!clk_data) {
+		iounmap(base);
+		return;
+	}
 
 	clk_data->base = base;
 	clk_data->clk_data.num = num_clks;
@@ -531,38 +535,7 @@ static int n5x_clkmgr_init(struct platform_device *pdev)
 	agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
 			      clk_data);
 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
-	return 0;
-}
-
-static int agilex_clkmgr_probe(struct platform_device *pdev)
-{
-	int (*probe_func)(struct platform_device *init_func);
-
-	probe_func = of_device_get_match_data(&pdev->dev);
-	if (!probe_func)
-		return -ENODEV;
-	return	probe_func(pdev);
 }
 
-static const struct of_device_id agilex_clkmgr_match_table[] = {
-	{ .compatible = "intel,agilex-clkmgr",
-	  .data = agilex_clkmgr_init },
-	{ .compatible = "intel,easic-n5x-clkmgr",
-	  .data = n5x_clkmgr_init },
-	{ }
-};
-
-static struct platform_driver agilex_clkmgr_driver = {
-	.probe		= agilex_clkmgr_probe,
-	.driver		= {
-		.name	= "agilex-clkmgr",
-		.suppress_bind_attrs = true,
-		.of_match_table = agilex_clkmgr_match_table,
-	},
-};
-
-static int __init agilex_clk_init(void)
-{
-	return platform_driver_register(&agilex_clkmgr_driver);
-}
-core_initcall(agilex_clk_init);
+CLK_OF_DECLARE(agilex_clkmgr, "intel,agilex-clkmgr", agilex_clkmgr_init);
+CLK_OF_DECLARE(n5x_clkmgr, "intel,easic-n5x-clkmgr", n5x_clkmgr_init);
-- 
2.49.GIT

Re: [PATCH 1/3] clk: socfpga: agilex: convert to CLK_OF_DECLARE()

[Brian Masney]

Hi Adrian,

On Fri, Sep 11, 2026 at 03:01:18PM +0800, adrian.ho.yin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> 
> Register Agilex and eASIC N5X clocks at of_clk_init() so they are
> available before platform devices probe.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> ---
>  drivers/clk/socfpga/clk-agilex.c | 83 +++++++++++---------------------
>  1 file changed, 28 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
> index 2bdea1997b5e..64a20c727d16 100644
> --- a/drivers/clk/socfpga/clk-agilex.c
> +++ b/drivers/clk/socfpga/clk-agilex.c
> @@ -4,8 +4,9 @@
>   */
>  #include <linux/slab.h>
>  #include <linux/clk-provider.h>
> +#include <linux/io.h>
>  #include <linux/of.h>
> -#include <linux/platform_device.h>
> +#include <linux/of_address.h>
>  
>  #include <dt-bindings/clock/agilex-clock.h>
>  
> @@ -454,24 +455,26 @@ static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks,
>  	return 0;
>  }
>  
> -static int agilex_clkmgr_init(struct platform_device *pdev)
> +static void __init agilex_clkmgr_init(struct device_node *np)
>  {
> -	struct device_node *np = pdev->dev.of_node;
> -	struct device *dev = &pdev->dev;
>  	struct stratix10_clock_data *clk_data;
>  	void __iomem *base;
>  	int i, num_clks;
>  
> -	base = devm_platform_ioremap_resource(pdev, 0);
> -	if (IS_ERR(base))
> -		return PTR_ERR(base);
> +	base = of_iomap(np, 0);
> +	if (!base) {
> +		pr_err("%s: failed to map clock registers\n", __func__);
> +		return;
> +	}
>  
>  	num_clks = AGILEX_NUM_CLKS;
>  
> -	clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
> -				num_clks), GFP_KERNEL);
> -	if (!clk_data)
> -		return -ENOMEM;
> +	clk_data = kzalloc(struct_size(clk_data, clk_data.hws, num_clks),
> +			   GFP_KERNEL);
> +	if (!clk_data) {
> +		iounmap(base);
> +		return;
> +	}
>  
>  	clk_data->clk_data.num = num_clks;
>  	clk_data->base = base;
> @@ -491,27 +494,28 @@ static int agilex_clkmgr_init(struct platform_device *pdev)
>  	agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
>  			      clk_data);
>  	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
> -	return 0;
>  }
>  
> -static int n5x_clkmgr_init(struct platform_device *pdev)
> +static void __init n5x_clkmgr_init(struct device_node *np)
>  {
> -	struct device_node *np = pdev->dev.of_node;
> -	struct device *dev = &pdev->dev;
>  	struct stratix10_clock_data *clk_data;
>  	void __iomem *base;
>  	int i, num_clks;
>  
> -	base = devm_platform_ioremap_resource(pdev, 0);
> -	if (IS_ERR(base))
> -		return PTR_ERR(base);
> +	base = of_iomap(np, 0);
> +	if (!base) {
> +		pr_err("%s: failed to map clock registers\n", __func__);
> +		return;
> +	}
>  
>  	num_clks = AGILEX_NUM_CLKS;
>  
> -	clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
> -				num_clks), GFP_KERNEL);
> -	if (!clk_data)
> -		return -ENOMEM;
> +	clk_data = kzalloc(struct_size(clk_data, clk_data.hws, num_clks),
> +			   GFP_KERNEL);
> +	if (!clk_data) {
> +		iounmap(base);
> +		return;
> +	}
>  
>  	clk_data->base = base;
>  	clk_data->clk_data.num = num_clks;
> @@ -531,38 +535,7 @@ static int n5x_clkmgr_init(struct platform_device *pdev)
>  	agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
>  			      clk_data);
>  	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
> -	return 0;
> -}
> -
> -static int agilex_clkmgr_probe(struct platform_device *pdev)
> -{
> -	int (*probe_func)(struct platform_device *init_func);
> -
> -	probe_func = of_device_get_match_data(&pdev->dev);
> -	if (!probe_func)
> -		return -ENODEV;
> -	return	probe_func(pdev);
>  }
>  
> -static const struct of_device_id agilex_clkmgr_match_table[] = {
> -	{ .compatible = "intel,agilex-clkmgr",
> -	  .data = agilex_clkmgr_init },
> -	{ .compatible = "intel,easic-n5x-clkmgr",
> -	  .data = n5x_clkmgr_init },
> -	{ }
> -};
> -
> -static struct platform_driver agilex_clkmgr_driver = {
> -	.probe		= agilex_clkmgr_probe,
> -	.driver		= {
> -		.name	= "agilex-clkmgr",
> -		.suppress_bind_attrs = true,
> -		.of_match_table = agilex_clkmgr_match_table,
> -	},
> -};
> -
> -static int __init agilex_clk_init(void)
> -{
> -	return platform_driver_register(&agilex_clkmgr_driver);
> -}
> -core_initcall(agilex_clk_init);
> +CLK_OF_DECLARE(agilex_clkmgr, "intel,agilex-clkmgr", agilex_clkmgr_init);
> +CLK_OF_DECLARE(n5x_clkmgr, "intel,easic-n5x-clkmgr", n5x_clkmgr_init);

Why do all of these clk providers need to be registered so early?
CLK_OF_DECLARE is abused quite a bit today and the majority of the clk
drivers that use it don't actually need it.

core_initcall() is pretty early as well. Can you use subsys_initcall
instead so that it's available by time the platform devices probe?

I recently introduced a subsys_platform_driver() macro to simplify the
code that should do what you need.

https://lore.kernel.org/linux-clk/20260908-subsys_initcall-v1-0-cbccf4cd4288@redhat.com/

Brian

[PATCH 2/3] clk: socfpga: agilex5: convert to CLK_OF_DECLARE()

[adrian.ho.yin.ng]

From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Register Agilex5 clocks at of_clk_init() so they are available before
platform devices probe.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 drivers/clk/socfpga/clk-agilex5.c | 56 +++++++++----------------------
 1 file changed, 15 insertions(+), 41 deletions(-)

diff --git a/drivers/clk/socfpga/clk-agilex5.c b/drivers/clk/socfpga/clk-agilex5.c
index f7f0ad884f64..fdbe13299800 100644
--- a/drivers/clk/socfpga/clk-agilex5.c
+++ b/drivers/clk/socfpga/clk-agilex5.c
@@ -5,8 +5,9 @@
  */
 #include <linux/slab.h>
 #include <linux/clk-provider.h>
+#include <linux/io.h>
 #include <linux/of.h>
-#include <linux/platform_device.h>
+#include <linux/of_address.h>
 #include  <dt-bindings/clock/intel,agilex5-clkmgr.h>
 #include "stratix10-clk.h"
 #include "clk.h"
@@ -486,24 +487,26 @@ static int agilex5_clk_register_pll(const struct agilex5_pll_clock *clks,
 	return 0;
 }
 
-static int agilex5_clkmgr_init(struct platform_device *pdev)
+static void __init agilex5_clkmgr_init(struct device_node *np)
 {
-	struct device_node *np = pdev->dev.of_node;
-	struct device *dev = &pdev->dev;
 	struct stratix10_clock_data *clk_data;
 	void __iomem *base;
 	int i, num_clks;
 
-	base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
+	base = of_iomap(np, 0);
+	if (!base) {
+		pr_err("%s: failed to map clock registers\n", __func__);
+		return;
+	}
 
 	num_clks = AGILEX5_NUM_CLKS;
 
-	clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
-				num_clks), GFP_KERNEL);
-	if (!clk_data)
-		return -ENOMEM;
+	clk_data = kzalloc(struct_size(clk_data, clk_data.hws, num_clks),
+			   GFP_KERNEL);
+	if (!clk_data) {
+		iounmap(base);
+		return;
+	}
 
 	clk_data->base = base;
 	clk_data->clk_data.num = num_clks;
@@ -527,35 +530,6 @@ static int agilex5_clkmgr_init(struct platform_device *pdev)
 				  ARRAY_SIZE(agilex5_gate_clks), clk_data);
 
 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
-	return 0;
-}
-
-static int agilex5_clkmgr_probe(struct platform_device *pdev)
-{
-	int (*probe_func)(struct platform_device *init_func);
-
-	probe_func = of_device_get_match_data(&pdev->dev);
-	if (!probe_func)
-		return -ENODEV;
-	return probe_func(pdev);
 }
 
-static const struct of_device_id agilex5_clkmgr_match_table[] = {
-	{ .compatible = "intel,agilex5-clkmgr", .data = agilex5_clkmgr_init },
-	{}
-};
-
-static struct platform_driver agilex5_clkmgr_driver = {
-	.probe		= agilex5_clkmgr_probe,
-	.driver		= {
-		.name	= "agilex5-clkmgr",
-		.suppress_bind_attrs = true,
-		.of_match_table = agilex5_clkmgr_match_table,
-	},
-};
-
-static int __init agilex5_clk_init(void)
-{
-	return platform_driver_register(&agilex5_clkmgr_driver);
-}
-core_initcall(agilex5_clk_init);
+CLK_OF_DECLARE(agilex5_clkmgr, "intel,agilex5-clkmgr", agilex5_clkmgr_init);
-- 
2.49.GIT

[PATCH 3/3] clk: socfpga: stratix10: convert to CLK_OF_DECLARE()

[adrian.ho.yin.ng]

From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Register Stratix10 clocks at of_clk_init() so they are available before
platform devices probe.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 drivers/clk/socfpga/clk-s10.c | 50 +++++++++--------------------------
 1 file changed, 13 insertions(+), 37 deletions(-)

diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index b4bf4e2d38e1..f97503dcf346 100644
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -4,8 +4,9 @@
  */
 #include <linux/slab.h>
 #include <linux/clk-provider.h>
+#include <linux/io.h>
 #include <linux/of.h>
-#include <linux/platform_device.h>
+#include <linux/of_address.h>
 
 #include <dt-bindings/clock/stratix10-clock.h>
 
@@ -382,25 +383,25 @@ static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
 	return 0;
 }
 
-static int s10_clkmgr_init(struct platform_device *pdev)
+static void __init s10_clkmgr_init(struct device_node *np)
 {
-	struct device_node *np = pdev->dev.of_node;
-	struct device *dev = &pdev->dev;
 	struct stratix10_clock_data *clk_data;
 	void __iomem *base;
 	int i, num_clks;
 
-	base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(base)) {
+	base = of_iomap(np, 0);
+	if (!base) {
 		pr_err("%s: failed to map clock registers\n", __func__);
-		return PTR_ERR(base);
+		return;
 	}
 
 	num_clks = STRATIX10_NUM_CLKS;
-	clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
-						 num_clks), GFP_KERNEL);
-	if (!clk_data)
-		return -ENOMEM;
+	clk_data = kzalloc(struct_size(clk_data, clk_data.hws, num_clks),
+			   GFP_KERNEL);
+	if (!clk_data) {
+		iounmap(base);
+		return;
+	}
 
 	clk_data->base = base;
 	clk_data->clk_data.num = num_clks;
@@ -421,31 +422,6 @@ static int s10_clkmgr_init(struct platform_device *pdev)
 			      clk_data);
 
 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
-	return 0;
-}
-
-static int s10_clkmgr_probe(struct platform_device *pdev)
-{
-	return	s10_clkmgr_init(pdev);
 }
 
-static const struct of_device_id stratix10_clkmgr_match_table[] = {
-	{ .compatible = "intel,stratix10-clkmgr",
-	  .data = s10_clkmgr_init },
-	{ }
-};
-
-static struct platform_driver stratix10_clkmgr_driver = {
-	.probe		= s10_clkmgr_probe,
-	.driver		= {
-		.name	= "stratix10-clkmgr",
-		.suppress_bind_attrs = true,
-		.of_match_table = stratix10_clkmgr_match_table,
-	},
-};
-
-static int __init s10_clk_init(void)
-{
-	return platform_driver_register(&stratix10_clkmgr_driver);
-}
-core_initcall(s10_clk_init);
+CLK_OF_DECLARE(stratix10_clkmgr, "intel,stratix10-clkmgr", s10_clkmgr_init);
-- 
2.49.GIT

Re: [PATCH 0/3] clk: socfpga: convert clock managers to CLK_OF_DECLARE()

[Dinh Nguyen]

On 9/11/26 02:01, adrian.ho.yin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> 
> The SoCFPGA Stratix10, Agilex, and Agilex5 clock managers are currently
> registered as platform drivers via core_initcall(). That is too late for
> early OF clock consumers: TIMER_OF_DECLARE callbacks run from time_init()
> before those drivers probe, and the DW APB timer cannot defer, so
> clk_get() fails and the timer is never brought up.
> 
> As discussed on the list [1], convert these drivers to CLK_OF_DECLARE()
> so the providers are registered from of_clk_init() and clocks are
> available before platform devices probe.
> 
> This series applies the same conversion to Agilex (including eASIC N5X),
> Agilex5, and Stratix10.
> 
> Boot-tested on Agilex7 (agilex7dksiagf014eb): dw_apb_timer registers as
> clocksource early, with no clk_get() failures.
> 
Please provide these details in each of the commits.

Thanks,
Dinh