From: Tong Tiangen <tongtiangen@huawei.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>, <Conor.Dooley@microchip.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<wangkefeng.wang@huawei.com>, Guohanjun <guohanjun@huawei.com>
Subject: Re: [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck
Date: Mon, 29 Aug 2022 09:26:22 +0800 [thread overview]
Message-ID: <bc23cce2-1a13-27c5-586b-283289ac8275@huawei.com> (raw)
In-Reply-To: <CAK8P3a0akgBkyVQuAfi5qdi9O5DhxZJ3FknxGH-gedpJpAVw6w@mail.gmail.com>
在 2022/8/27 20:49, Arnd Bergmann 写道:
> On Sat, Aug 27, 2022 at 12:43 PM Tong Tiangen <tongtiangen@huawei.com> wrote:
>> 在 2022/8/26 17:30, Arnd Bergmann 写道:
>>
>> I am very interested in the implementation of X86. I need to investigate
>> and consider a cross architecture implementation.
>
> One more point about the cross-architecture work: it generally makes
> sense to do the most commonly used architectures first, usually
> that would be x86, arm64 and powerpc64, followed by riscv, arm,
> s390 and mips. If we can find something that the first architecture
> maintainers like, everyone else can follow and you don't have to
> rework all of them multiple times before getting to a consensus.
>
>> However, I understand that the modification of the current patch has
>> little to do with the two points mentioned above. We can optimize the
>> code step by step.
>
> You are correct that this has little to do with your patch, my point
> was mainly that your patch is moving the code further away from
> the other architectures, so it would make it harder to then do the
> changes we actually want.
>
> Arnd
I understand what you mean,it's reasonable.
Thanks,
Tong.
>
> .
next prev parent reply other threads:[~2022-08-29 1:26 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-15 3:20 [PATCH -next v2 0/2]riscv: some refactorings realted to uaccess and extable Tong Tiangen
2022-08-15 3:20 ` [PATCH -next v2 1/2] riscv: uaccess: rename __get/put_user_nocheck to __get/put_mem_nocheck Tong Tiangen
2022-08-25 10:56 ` Andrew Jones
2022-08-26 6:33 ` Tong Tiangen
2022-08-26 7:43 ` Andrew Jones
2022-08-27 10:39 ` Tong Tiangen
2022-08-26 9:30 ` Arnd Bergmann
2022-08-27 10:43 ` Tong Tiangen
2022-08-27 12:49 ` Arnd Bergmann
2022-08-29 1:26 ` Tong Tiangen [this message]
2022-08-15 3:20 ` [PATCH -next v2 2/2] riscv: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support Tong Tiangen
2022-08-25 11:06 ` Andrew Jones
2022-08-26 6:44 ` Tong Tiangen
2022-08-26 8:16 ` Andrew Jones
2022-08-27 10:39 ` Tong Tiangen
2022-09-21 20:25 ` Palmer Dabbelt
2022-10-21 12:23 ` Tong Tiangen
2022-08-24 6:31 ` [PATCH -next v2 0/2]riscv: some refactorings realted to uaccess and extable Tong Tiangen
2022-08-24 16:49 ` Conor.Dooley
2022-08-25 3:04 ` Tong Tiangen
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