From: Neil Armstrong <neil.armstrong@linaro.org>
To: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Algea Cao <algea.cao@rock-chips.com>,
Dmitry Baryshkov <lumag@kernel.org>
Cc: kernel@collabora.com, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment
Date: Tue, 13 Jan 2026 09:11:54 +0100 [thread overview]
Message-ID: <bc3d3416-2f7c-4f4a-a90e-2b3d086ff568@linaro.org> (raw)
In-Reply-To: <20260113-phy-hdptx-frl-v6-3-8d5f97419c0b@collabora.com>
On 1/13/26 00:20, Cristian Ciocaltea wrote:
> Handle a bunch of reported checkpatch.pl complaints:
>
> CHECK: Alignment should match open parenthesis
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index 89710066d70c..3f8a7f4f5cd8 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> @@ -1624,11 +1624,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
> regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
> LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
> FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
> - ctrl->tx_jeq_even_ctrl));
> + ctrl->tx_jeq_even_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset,
> LN_TX_JEQ_ODD_CTRL_RBR_MASK,
> FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK,
> - ctrl->tx_jeq_odd_ctrl));
> + ctrl->tx_jeq_odd_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
> LN_TX_SER_40BIT_EN_RBR_MASK,
> FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1));
> @@ -1638,11 +1638,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
> regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
> LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
> FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
> - ctrl->tx_jeq_even_ctrl));
> + ctrl->tx_jeq_even_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
> LN_TX_JEQ_ODD_CTRL_HBR_MASK,
> FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK,
> - ctrl->tx_jeq_odd_ctrl));
> + ctrl->tx_jeq_odd_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
> LN_TX_SER_40BIT_EN_HBR_MASK,
> FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1));
> @@ -1653,11 +1653,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
> regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
> LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
> FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
> - ctrl->tx_jeq_even_ctrl));
> + ctrl->tx_jeq_even_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
> LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
> FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
> - ctrl->tx_jeq_odd_ctrl));
> + ctrl->tx_jeq_odd_ctrl));
> regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
> LN_TX_SER_40BIT_EN_HBR2_MASK,
> FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1));
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
next prev parent reply other threads:[~2026-01-13 8:12 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-12 23:20 [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 01/11] phy: hdmi: Add HDMI 2.1 FRL configuration options Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 02/11] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay() Cristian Ciocaltea
2026-01-13 8:13 ` Neil Armstrong
2026-01-12 23:20 ` [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment Cristian Ciocaltea
2026-01-13 8:11 ` Neil Armstrong [this message]
2026-01-12 23:20 ` [PATCH v6 04/11] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes Cristian Ciocaltea
2026-01-13 8:12 ` Neil Armstrong
2026-01-12 23:20 ` [PATCH v6 05/11] phy: rockchip: samsung-hdptx: Enable lane output in common helper Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 06/11] phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 07/11] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 08/11] phy: rockchip: samsung-hdptx: Drop hw_rate driver data Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 09/11] phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 10/11] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper Cristian Ciocaltea
2026-01-12 23:20 ` [PATCH v6 11/11] phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support Cristian Ciocaltea
2026-01-21 8:52 ` [PATCH v6 00/11] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Vinod Koul
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