From: "Chen, Zide" <zide.chen@intel.com>
To: Guixiong Wei <weiguixiong@bytedance.com>, peterz@infradead.org
Cc: Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
James Clark <james.clark@linaro.org>,
Thomas Gleixner <tglx@kernel.org>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] perf/x86/intel/uncore: Fix DMR CXL CM invert filter
Date: Thu, 8 Oct 2026 10:12:40 -0500 [thread overview]
Message-ID: <bcb837c5-8a8d-4cba-9c14-73275c5a7bb0@intel.com> (raw)
In-Reply-To: <20261008051953.6293-2-weiguixiong@bytedance.com>
On 10/8/2026 12:19 AM, Guixiong Wei wrote:
> The DMR CXL CM PMU places its invert filter at config bit 21 and its
> 9-bit threshold at bits 23-31. However, dmr_uncore_cxlcm uses
> GENERIC_PMON_RAW_EVENT_MASK, which covers the threshold through the
> generic bit 23 invert field and bits 24-31 threshold field, but does not
> include the relocated invert bit. As a result, uncore_pmu_event_init()
> silently clears bit 21 and inv=1 programs the same configuration as
> inv=0.
>
> Add bit 21 to a DMR CXL CM-specific event mask so the requested invert
> filter reaches hardware.
>
> Fixes: 6daf2c35b835 ("perf/x86/intel/uncore: Add IMH PMON support for Diamond Rapids")
> Signed-off-by: Guixiong Wei <weiguixiong@bytedance.com>
> ---
> arch/x86/events/intel/uncore_snbep.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index a97cd029db366..1b460cf27a10f 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -474,6 +474,9 @@
> /* DMR */
> #define DMR_IMH1_HIOP_MMIO_BASE 0x1ffff6ae7000
> #define DMR_HIOP_MMIO_SIZE 0x8000
> +#define DMR_CXLCM_PMON_CTL_INVERT BIT(21)
> +#define DMR_CXLCM_PMON_RAW_EVENT_MASK (GENERIC_PMON_RAW_EVENT_MASK | \
> + DMR_CXLCM_PMON_CTL_INVERT)
> #define DMR_CXLCM_EVENT_MASK_EXT 0xf
> #define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff
> #define DMR_PCIE4_EVENT_MASK_EXT 0xffffff
> @@ -6696,7 +6699,7 @@ static struct event_constraint dmr_uncore_cxlcm_constraints[] = {
>
> static struct intel_uncore_type dmr_uncore_cxlcm = {
> .name = "cxlcm",
> - .event_mask = GENERIC_PMON_RAW_EVENT_MASK,
> + .event_mask = DMR_CXLCM_PMON_RAW_EVENT_MASK,
Thanks for the fix!
Reviewed-by: Zide Chen <zide.chen@intel.com>
> .event_mask_ext = DMR_CXLCM_EVENT_MASK_EXT,
> .constraints = dmr_uncore_cxlcm_constraints,
> .format_group = &dmr_cxlcm_uncore_format_group,
prev parent reply other threads:[~2026-10-08 15:12 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-08 5:19 Guixiong Wei
2026-10-08 15:12 ` Chen, Zide [this message]
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