[PATCH] perf/x86/intel/uncore: Fix DMR CXL CM invert filter

[PATCH] perf/x86/intel/uncore: Fix DMR CXL CM invert filter

[Guixiong Wei]

The DMR CXL CM PMU places its invert filter at config bit 21 and its
9-bit threshold at bits 23-31. However, dmr_uncore_cxlcm uses
GENERIC_PMON_RAW_EVENT_MASK, which covers the threshold through the
generic bit 23 invert field and bits 24-31 threshold field, but does not
include the relocated invert bit. As a result, uncore_pmu_event_init()
silently clears bit 21 and inv=1 programs the same configuration as
inv=0.

Add bit 21 to a DMR CXL CM-specific event mask so the requested invert
filter reaches hardware.

Fixes: 6daf2c35b835 ("perf/x86/intel/uncore: Add IMH PMON support for Diamond Rapids")
Signed-off-by: Guixiong Wei <weiguixiong@bytedance.com>
---
 arch/x86/events/intel/uncore_snbep.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index a97cd029db366..1b460cf27a10f 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -474,6 +474,9 @@
 /* DMR */
 #define DMR_IMH1_HIOP_MMIO_BASE			0x1ffff6ae7000
 #define DMR_HIOP_MMIO_SIZE			0x8000
+#define DMR_CXLCM_PMON_CTL_INVERT		BIT(21)
+#define DMR_CXLCM_PMON_RAW_EVENT_MASK		(GENERIC_PMON_RAW_EVENT_MASK | \
+						 DMR_CXLCM_PMON_CTL_INVERT)
 #define DMR_CXLCM_EVENT_MASK_EXT		0xf
 #define DMR_HAMVF_EVENT_MASK_EXT		0xffffffff
 #define DMR_PCIE4_EVENT_MASK_EXT		0xffffff
@@ -6696,7 +6699,7 @@ static struct event_constraint dmr_uncore_cxlcm_constraints[] = {
 
 static struct intel_uncore_type dmr_uncore_cxlcm = {
 	.name			= "cxlcm",
-	.event_mask		= GENERIC_PMON_RAW_EVENT_MASK,
+	.event_mask		= DMR_CXLCM_PMON_RAW_EVENT_MASK,
 	.event_mask_ext		= DMR_CXLCM_EVENT_MASK_EXT,
 	.constraints		= dmr_uncore_cxlcm_constraints,
 	.format_group		= &dmr_cxlcm_uncore_format_group,
-- 
2.50.1 (Apple Git-155)

Re: [PATCH] perf/x86/intel/uncore: Fix DMR CXL CM invert filter

[Chen, Zide]

On 10/8/2026 12:19 AM, Guixiong Wei wrote:
> The DMR CXL CM PMU places its invert filter at config bit 21 and its
> 9-bit threshold at bits 23-31. However, dmr_uncore_cxlcm uses
> GENERIC_PMON_RAW_EVENT_MASK, which covers the threshold through the
> generic bit 23 invert field and bits 24-31 threshold field, but does not
> include the relocated invert bit. As a result, uncore_pmu_event_init()
> silently clears bit 21 and inv=1 programs the same configuration as
> inv=0.
> 
> Add bit 21 to a DMR CXL CM-specific event mask so the requested invert
> filter reaches hardware.
> 
> Fixes: 6daf2c35b835 ("perf/x86/intel/uncore: Add IMH PMON support for Diamond Rapids")
> Signed-off-by: Guixiong Wei <weiguixiong@bytedance.com>
> ---
>  arch/x86/events/intel/uncore_snbep.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index a97cd029db366..1b460cf27a10f 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -474,6 +474,9 @@
>  /* DMR */
>  #define DMR_IMH1_HIOP_MMIO_BASE			0x1ffff6ae7000
>  #define DMR_HIOP_MMIO_SIZE			0x8000
> +#define DMR_CXLCM_PMON_CTL_INVERT		BIT(21)
> +#define DMR_CXLCM_PMON_RAW_EVENT_MASK		(GENERIC_PMON_RAW_EVENT_MASK | \
> +						 DMR_CXLCM_PMON_CTL_INVERT)
>  #define DMR_CXLCM_EVENT_MASK_EXT		0xf
>  #define DMR_HAMVF_EVENT_MASK_EXT		0xffffffff
>  #define DMR_PCIE4_EVENT_MASK_EXT		0xffffff
> @@ -6696,7 +6699,7 @@ static struct event_constraint dmr_uncore_cxlcm_constraints[] = {
>  
>  static struct intel_uncore_type dmr_uncore_cxlcm = {
>  	.name			= "cxlcm",
> -	.event_mask		= GENERIC_PMON_RAW_EVENT_MASK,
> +	.event_mask		= DMR_CXLCM_PMON_RAW_EVENT_MASK,

Thanks for the fix!

Reviewed-by: Zide Chen <zide.chen@intel.com>


>  	.event_mask_ext		= DMR_CXLCM_EVENT_MASK_EXT,
>  	.constraints		= dmr_uncore_cxlcm_constraints,
>  	.format_group		= &dmr_cxlcm_uncore_format_group,