From: Stephane Eranian <eranian@google.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: linux-kernel@vger.kernel.org, mingo@elte.hu, paulus@samba.org,
davem@davemloft.net, fweisbec@gmail.com, robert.richter@amd.com,
perfmon2-devel@lists.sf.net, eranian@gmail.com
Subject: Re: [PATCH] perf_events: AMD event scheduling (v2)
Date: Thu, 4 Feb 2010 16:04:17 +0100 [thread overview]
Message-ID: <bd4cb8901002040704vcd2d8feo82e2e1c166a02669@mail.gmail.com> (raw)
In-Reply-To: <1265295545.24455.2270.camel@laptop>
On Thu, Feb 4, 2010 at 3:59 PM, Peter Zijlstra <peterz@infradead.org> wrote:
>
> On Thu, 2010-02-04 at 15:55 +0100, Peter Zijlstra wrote:
> > > + if (boot_cpu_data.x86_max_cores < 2)
> > > + return;
> >
> > So there are no single core AMD chips that have a NorthBridge PMU? What
> > about the recent 64bit single core laptop chips?
>
> D'0h, for those there is no need to create inter-cpu constraints.
>
Exactly!
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next prev parent reply other threads:[~2010-02-04 15:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-02-01 20:15 Stephane Eranian
2010-02-04 14:55 ` Peter Zijlstra
2010-02-04 14:59 ` Peter Zijlstra
2010-02-04 15:04 ` Stephane Eranian [this message]
2010-02-04 16:05 ` Stephane Eranian
2010-02-04 16:19 ` Peter Zijlstra
2010-02-04 16:32 ` Stephane Eranian
2010-02-04 16:35 ` Stephane Eranian
2010-02-25 18:29 ` Stephane Eranian
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