Re: [PATCH] perf_events: AMD event scheduling (v2)

[Stephane Eranian <eranian@google.com>]

>> What I'm worried about is:
>>
>> CPU A and B are of the same NorthBridge and all node counters are taken.
>>
>> CPU-A                   CPU-B
>>
>> perf_disable();
>> event->pmu->disable(event)
>>  x86_pmu.put_event_constraint() /* free slot n */
>>
>>                        event->pmu->enable(event);
>>                          x86_schedule_events();
>>                            x86_pmu.get_event_constraint() /* grab slot n */
>>
>> event->pmu->enable(event)
>>  x86_schedule_events()
>>    x86_pmu.get_event_constraint() /* FAIL */
>> perf_enable();
>>
>> That means you cannot disable/enable the same event within a
>> perf_disable/enable section.
>>
> Yes but I would say that is because of the logic behind the enable/disable
> interface. Here you are disabling "for a short period", you know you're going
> to re-enable. Yet you are using an API that is a generic enable/disable.
> You would need to pass some argument to disable() to say "temporary"
> or "stop but don't release the resource".
>
I think if you were to distinguish between "stop the counter", and
"free the counter"
things would work better here.