From: Stephen Boyd <sboyd@kernel.org>
To: Devi Priya <quic_devipriy@quicinc.com>,
agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
mturquette@baylibre.com
Cc: quic_saahtoma@quicinc.com
Subject: Re: [PATCH] clk: qcom: clk-rcg2: Fix wrong RCG clock rate for high parent frequencies
Date: Thu, 20 Jul 2023 11:07:07 -0700 [thread overview]
Message-ID: <be0893d1082bba7c3c8c499f9eedbfa5.sboyd@kernel.org> (raw)
In-Reply-To: <20230720083304.28881-1-quic_devipriy@quicinc.com>
Quoting Devi Priya (2023-07-20 01:33:04)
> If the parent clock rate is greater than unsigned long max/2 then
> integer overflow happens when calculating the clock rate on 32-bit systems.
> As RCG2 uses half integer dividers, the clock rate is first being
> multiplied by 2 which will overflow the unsigned long max value. So, use
> unsigned long long for rate computations to avoid overflow.
>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
Any Fixes tag?
next prev parent reply other threads:[~2023-07-20 18:07 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 8:33 Devi Priya
2023-07-20 16:08 ` Konrad Dybcio
2023-07-20 16:08 ` Konrad Dybcio
2023-07-20 18:07 ` Stephen Boyd [this message]
2023-07-20 19:07 ` Marijn Suijten
2023-08-30 8:40 ` Devi Priya
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