Re: [PATCH] clk: qcom: clk-rcg2: Fix wrong RCG clock rate for high parent frequencies

[Konrad Dybcio <konrad.dybcio@linaro.org>]

On 20.07.2023 18:08, Konrad Dybcio wrote:
> On 20.07.2023 10:33, Devi Priya wrote:
>> If the parent clock rate is greater than unsigned long max/2 then
>> integer overflow happens when calculating the clock rate on 32-bit systems.
>> As RCG2 uses half integer dividers, the clock rate is first being
>> multiplied by 2 which will overflow the unsigned long max value. So, use
>> unsigned long long for rate computations to avoid overflow.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>>  drivers/clk/qcom/clk-rcg2.c | 12 ++++++------
>>  1 file changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
>> index e22baf3a7112..42d00b134975 100644
>> --- a/drivers/clk/qcom/clk-rcg2.c
>> +++ b/drivers/clk/qcom/clk-rcg2.c
>> @@ -156,18 +156,18 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
>>   *            hid_div       n
>>   */
>>  static unsigned long
>> -calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
>> +calc_rate(unsigned long parent_rate, u32 m, u32 n, u32 mode, u32 hid_div)
>>  {
>> +	u64 rate = parent_rate;
> This should not be necessary.. You're being passed a copy of
> the original value, which you can operate on.
> 
> Otherwise, LGTM
Well obviously no, as I hit enter I realized this is of a different
type..

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad