From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Xilin Wu <sophon@radxa.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dragon@radxa.com
Subject: Re: [PATCH] arm64: dts: qcom: sc8280xp: Fix GPU SMMU context fault interrupts
Date: Wed, 14 Oct 2026 10:59:45 +0200 [thread overview]
Message-ID: <bf865b13-4773-45d6-a93b-4db4f77b1feb@oss.qualcomm.com> (raw)
In-Reply-To: <20261013-sc8280xp-gpu-smmu-fix-v1-1-8a781e3f1554@radxa.com>
On 10/13/26 11:59 AM, Xilin Wu wrote:
> The GPU SMMU interrupt list includes PMU interrupts as the first two
> context fault interrupts. This makes the driver register the fault
> handlers for context banks 0 and 1 on SPIs 678 and 679 instead of 680
> and 681. Translation faults are consequently left unhandled, which
> can stall the GPU and prevent recovery.
the context interrupts are 680-688 and 703
Konrad
next prev parent reply other threads:[~2026-10-14 8:59 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 9:59 Xilin Wu
2026-10-14 8:42 ` Abel Vesa
2026-10-14 8:59 ` Konrad Dybcio [this message]
2026-10-14 9:11 ` Xilin Wu
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