[PATCH] arm64: dts: qcom: sc8280xp: Fix GPU SMMU context fault interrupts

[PATCH] arm64: dts: qcom: sc8280xp: Fix GPU SMMU context fault interrupts

[Xilin Wu]

The GPU SMMU interrupt list includes PMU interrupts as the first two
context fault interrupts. This makes the driver register the fault
handlers for context banks 0 and 1 on SPIs 678 and 679 instead of 680
and 681. Translation faults are consequently left unhandled, which
can stall the GPU and prevent recovery.

List SPIs 680 through 686 in context bank order to match the seven
context banks exposed to non-secure software.

Fixes: eec51ab2fd6f ("arm64: dts: qcom: sc8280xp: Add GPU related nodes")
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index fbcfd3883bbb..504ba6618bc7 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3533,18 +3533,13 @@ gpu_smmu: iommu@3da0000 {
 			#global-interrupts = <2>;
 			interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>;
 
 			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
 				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,

---
base-commit: a90ee4305c4a5df72c11b31dacfdc76e00fcf78a
change-id: 20261013-sc8280xp-gpu-smmu-fix-e07e4a2ed7b2

Best regards,
--  
Xilin Wu <sophon@radxa.com>

Re: [PATCH] arm64: dts: qcom: sc8280xp: Fix GPU SMMU context fault interrupts

[Abel Vesa]

On 26-10-13 17:59:19, Xilin Wu wrote:
> The GPU SMMU interrupt list includes PMU interrupts as the first two
> context fault interrupts. This makes the driver register the fault
> handlers for context banks 0 and 1 on SPIs 678 and 679 instead of 680
> and 681. Translation faults are consequently left unhandled, which
> can stall the GPU and prevent recovery.
> 
> List SPIs 680 through 686 in context bank order to match the seven
> context banks exposed to non-secure software.
> 
> Fixes: eec51ab2fd6f ("arm64: dts: qcom: sc8280xp: Add GPU related nodes")
> Signed-off-by: Xilin Wu <sophon@radxa.com>

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [PATCH] arm64: dts: qcom: sc8280xp: Fix GPU SMMU context fault interrupts

[Konrad Dybcio]

On 10/13/26 11:59 AM, Xilin Wu wrote:
> The GPU SMMU interrupt list includes PMU interrupts as the first two
> context fault interrupts. This makes the driver register the fault
> handlers for context banks 0 and 1 on SPIs 678 and 679 instead of 680
> and 681. Translation faults are consequently left unhandled, which
> can stall the GPU and prevent recovery.

the context interrupts are 680-688 and 703

Konrad

Re: [PATCH] arm64: dts: qcom: sc8280xp: Fix GPU SMMU context fault interrupts

[Xilin Wu]

On 10/14/2026 4:59 PM, Konrad Dybcio wrote:
> On 10/13/26 11:59 AM, Xilin Wu wrote:
>> The GPU SMMU interrupt list includes PMU interrupts as the first two
>> context fault interrupts. This makes the driver register the fault
>> handlers for context banks 0 and 1 on SPIs 678 and 679 instead of 680
>> and 681. Translation faults are consequently left unhandled, which
>> can stall the GPU and prevent recovery.
> 
> the context interrupts are 680-688 and 703
> 
> Konrad

Thanks for the clarification. I limited the list to seven because IDR1 
reports NUMCB=7 on my board. However, DT should describe the full 
hardware interrupt list, and arm-smmu already ignores entries beyond the 
reported context-bank count. In EL2, IDR1 does report NUMCB=10. I'll 
include SPIs 680–688 and 703 in v2.

-- 
Best regards,
Xilin Wu <sophon@radxa.com>