From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Mike Leach <mike.leach@linaro.org>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: mathieu.poirier@linaro.org, peterz@infradead.org,
mingo@redhat.com, acme@kernel.org,
linux-perf-users@vger.kernel.org, leo.yan@linaro.org,
quic_jinlmao@quicinc.com
Subject: Re: [PATCH v5 06/14] coresight: etm3x: Update ETM3 driver to use Trace ID API
Date: Tue, 8 Nov 2022 22:25:45 +0000 [thread overview]
Message-ID: <bffacfbb-9623-4aa9-a3f7-6c850b8941bc@arm.com> (raw)
In-Reply-To: <20221101163103.17921-7-mike.leach@linaro.org>
On 01/11/2022 16:30, Mike Leach wrote:
> Use the TraceID API to allocate ETM trace IDs dynamically.
>
> As with the etm4x we allocate on enable / disable for perf,
> allocate on enable / reset for sysfs.
>
> Additionally we allocate on sysfs file read as both perf and sysfs
> can read the ID before enabling the hardware.
>
> Remove sysfs option to write trace ID - which is inconsistent with
> both the dynamic allocation method and the fixed allocation method
> previously used.
>
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
> drivers/hwtracing/coresight/coresight-etm.h | 2 +
> .../coresight/coresight-etm3x-core.c | 69 +++++++++++++++++--
> .../coresight/coresight-etm3x-sysfs.c | 27 ++------
> 3 files changed, 72 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
> index f3ab96eaf44e..3667428d38b6 100644
> --- a/drivers/hwtracing/coresight/coresight-etm.h
> +++ b/drivers/hwtracing/coresight/coresight-etm.h
> @@ -287,4 +287,6 @@ int etm_get_trace_id(struct etm_drvdata *drvdata);
> void etm_set_default(struct etm_config *config);
> void etm_config_trace_mode(struct etm_config *config);
> struct etm_config *get_etm_config(struct etm_drvdata *drvdata);
> +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata);
> +void etm_release_trace_id(struct etm_drvdata *drvdata);
> #endif
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> index d0ab9933472b..9a7a9e974d41 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> @@ -32,6 +32,7 @@
>
> #include "coresight-etm.h"
> #include "coresight-etm-perf.h"
> +#include "coresight-trace-id.h"
>
> /*
> * Not really modular but using module_param is the easiest way to
> @@ -490,16 +491,59 @@ static int etm_trace_id(struct coresight_device *csdev)
> return etm_get_trace_id(drvdata);
> }
>
> +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata)
> +{
> + int trace_id;
> +
> + /*
> + * This will allocate a trace ID to the cpu,
> + * or return the one currently allocated.
> + *
> + * trace id function has its own lock
> + */
> + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
> + if (IS_VALID_ID(trace_id))
> + drvdata->traceid = (u8)trace_id;
> + else
> + dev_err(&drvdata->csdev->dev,
> + "Failed to allocate trace ID for %s on CPU%d\n",
> + dev_name(&drvdata->csdev->dev), drvdata->cpu);
> + return trace_id;
> +}
> +
> +void etm_release_trace_id(struct etm_drvdata *drvdata)
> +{
> + coresight_trace_id_put_cpu_id(drvdata->cpu);
> +}
> +
> static int etm_enable_perf(struct coresight_device *csdev,
> struct perf_event *event)
> {
> struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + int trace_id;
>
> if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
> return -EINVAL;
>
> /* Configure the tracer based on the session's specifics */
> etm_parse_event_config(drvdata, event);
> +
> + /*
> + * perf allocates cpu ids as part of _setup_aux() - device needs to use
> + * the allocated ID. This reads the current version without allocation.
> + *
> + * This does not use the trace id lock to prevent lock_dep issues
> + * with perf locks - we know the ID cannot change until perf shuts down
> + * the session
> + */
> + trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu);
> + if (!IS_VALID_ID(trace_id)) {
> + dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
> + dev_name(&drvdata->csdev->dev), drvdata->cpu);
> + return -EINVAL;
> + }
> + drvdata->traceid = (u8)trace_id;
> +
> /* And enable it */
> return etm_enable_hw(drvdata);
> }
> @@ -512,6 +556,11 @@ static int etm_enable_sysfs(struct coresight_device *csdev)
>
> spin_lock(&drvdata->spinlock);
>
> + /* sysfs needs to allocate and set a trace ID */
> + ret = etm_read_alloc_trace_id(drvdata);
> + if (ret < 0)
> + goto unlock_enable_sysfs;
> +
> /*
> * Configure the ETM only if the CPU is online. If it isn't online
> * hw configuration will take place on the local CPU during bring up.
> @@ -528,6 +577,10 @@ static int etm_enable_sysfs(struct coresight_device *csdev)
> ret = -ENODEV;
> }
>
> + if (ret)
> + etm_release_trace_id(drvdata);
> +
> +unlock_enable_sysfs:
> spin_unlock(&drvdata->spinlock);
>
> if (!ret)
> @@ -611,6 +664,9 @@ static void etm_disable_perf(struct coresight_device *csdev)
> coresight_disclaim_device_unlocked(csdev);
>
> CS_LOCK(drvdata->base);
> +
> + /* perf will release trace ids when _free_aux() is called at the end of the session */
Minor nit: Please split the line.
With that
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
next prev parent reply other threads:[~2022-11-08 22:29 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 16:30 [PATCH v5 00/14] coresight: Add new API to allocate trace source ID values Mike Leach
2022-11-01 16:30 ` [PATCH v5 01/14] coresight: trace-id: Add API to dynamically assign Trace " Mike Leach
2022-11-08 14:03 ` Suzuki K Poulose
2022-11-22 9:28 ` Mike Leach
2022-11-08 19:14 ` Suzuki K Poulose
2022-11-01 16:30 ` [PATCH v5 02/14] coresight: Remove obsolete Trace ID unniqueness checks Mike Leach
2022-11-01 16:30 ` [PATCH v5 03/14] coresight: perf: traceid: Add perf ID allocation and notifiers Mike Leach
2022-11-08 15:04 ` Suzuki Kuruppassery Poulose
2022-11-01 16:30 ` [PATCH v5 04/14] coresight: stm: Update STM driver to use Trace ID API Mike Leach
2022-11-01 16:30 ` [PATCH v5 05/14] coresight: etm4x: Update ETM4 " Mike Leach
2022-11-08 22:24 ` Suzuki K Poulose
2022-11-01 16:30 ` [PATCH v5 06/14] coresight: etm3x: Update ETM3 " Mike Leach
2022-11-08 22:25 ` Suzuki K Poulose [this message]
2022-11-01 16:30 ` [PATCH v5 07/14] coresight: etmX.X: stm: Remove trace_id() callback Mike Leach
2022-11-01 16:30 ` [PATCH v5 08/14] coresight: trace id: Remove legacy get trace ID function Mike Leach
2022-11-08 17:06 ` Suzuki Kuruppassery Poulose
2022-11-01 16:30 ` [PATCH v5 09/14] perf: cs-etm: Move mapping of Trace ID and cpu into helper function Mike Leach
2022-11-08 23:31 ` Suzuki K Poulose
2022-11-01 16:30 ` [PATCH v5 10/14] perf: cs-etm: Update record event to use new Trace ID protocol Mike Leach
2022-11-08 23:31 ` Suzuki K Poulose
2022-11-01 16:31 ` [PATCH v5 11/14] kernel: events: Export perf_report_aux_output_id() Mike Leach
2022-11-01 16:31 ` [PATCH v5 12/14] perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet Mike Leach
2022-11-09 12:00 ` Suzuki Kuruppassery Poulose
2022-11-01 16:31 ` [PATCH v5 13/14] coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID Mike Leach
2022-11-08 22:49 ` Suzuki K Poulose
2022-11-01 16:31 ` [PATCH v5 14/14] coresight: trace-id: Add debug & test macros to Trace ID allocation Mike Leach
2022-11-09 12:07 ` Suzuki Kuruppassery Poulose
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