[PATCH v2 0/2] Add interconnect support for Qualcomm Mahua SoC

[PATCH v2 0/2] Add interconnect support for Qualcomm Mahua SoC

[Raviteja Laggyshetty]

Mahua is a derivative of the Glymur SoC and shares a significant 
portion of its interconnect topology with Glymur. As such, this 
series extends the existing Glymur interconnect driver to support 
Mahua, reusing common definitions where possible and adding 
SoC-specific configurations where necessary.

Device tree changes aren't part of this series and will be posted
separately.

---
Changes in v2:
- Reuse the Glymur device data for Mahua and override with Mahua
  specific values [Dmitry]
- Update the commit text to be imperative [Dmitry]
- Link to v1: https://lore.kernel.org/r/20260123-mahua_icc-v1-0-bc82cb087f1e@oss.qualcomm.com

---
Raviteja Laggyshetty (2):
      dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC
      interconnect: qcom: glymur: Add Mahua SoC support

 .../bindings/interconnect/qcom,glymur-rpmh.yaml    | 132 +++++++++++++++++----
 drivers/interconnect/qcom/glymur.c                 |  38 +++++-
 2 files changed, 142 insertions(+), 28 deletions(-)
---
base-commit: 6cd6c12031130a349a098dbeb19d8c3070d2dfbe
change-id: 20260120-mahua_icc-76054966880b

Best regards,
-- 
Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>

[PATCH v2 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC

[Raviteja Laggyshetty]

Document the RPMh Network-on-Chip (NoC) interconnect for the Qualcomm
Mahua platform.

Mahua is a derivative of the Glymur SoC. Many interconnect nodes are
identical and continue to use Glymur fallback compatibles. Mahua
introduces SoC-specific configurations and topologies for several
NoC blocks, including CNOC, HSCNOC, PCIe West ANoC/Slave NoCs.
This updates the existing Glymur yaml schema to include Mahua-specific
compatible strings, using two-cell "fallback" compatibles wherever
the hardware is identical with Glymur.

Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
 .../bindings/interconnect/qcom,glymur-rpmh.yaml    | 132 +++++++++++++++++----
 1 file changed, 109 insertions(+), 23 deletions(-)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
index d55a7bcf5591eea79c173a12b12c659321ca3c2e..723ae547ae06073b7fa93dc7a94f33336068519b 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR
+title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur and Mahua SoCs
 
 maintainers:
   - Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
@@ -21,28 +21,98 @@ description: |
 
 properties:
   compatible:
-    enum:
-      - qcom,glymur-aggre1-noc
-      - qcom,glymur-aggre2-noc
-      - qcom,glymur-aggre3-noc
-      - qcom,glymur-aggre4-noc
-      - qcom,glymur-clk-virt
-      - qcom,glymur-cnoc-cfg
-      - qcom,glymur-cnoc-main
-      - qcom,glymur-hscnoc
-      - qcom,glymur-lpass-ag-noc
-      - qcom,glymur-lpass-lpiaon-noc
-      - qcom,glymur-lpass-lpicx-noc
-      - qcom,glymur-mc-virt
-      - qcom,glymur-mmss-noc
-      - qcom,glymur-nsinoc
-      - qcom,glymur-nsp-noc
-      - qcom,glymur-oobm-ss-noc
-      - qcom,glymur-pcie-east-anoc
-      - qcom,glymur-pcie-east-slv-noc
-      - qcom,glymur-pcie-west-anoc
-      - qcom,glymur-pcie-west-slv-noc
-      - qcom,glymur-system-noc
+    oneOf:
+      - items:
+          - enum:
+              - qcom,mahua-clk-virt
+          - const: qcom,glymur-clk-virt
+      - items:
+          - enum:
+              - qcom,mahua-cnoc-main
+          - const: qcom,glymur-cnoc-main
+      - items:
+          - enum:
+              - qcom,mahua-system-noc
+          - const: qcom,glymur-system-noc
+      - items:
+          - enum:
+              - qcom,mahua-pcie-east-anoc
+          - const: qcom,glymur-pcie-east-anoc
+      - items:
+          - enum:
+              - qcom,mahua-aggre1-noc
+          - const: qcom,glymur-aggre1-noc
+      - items:
+          - enum:
+              - qcom,mahua-aggre2-noc
+          - const: qcom,glymur-aggre2-noc
+      - items:
+          - enum:
+              - qcom,mahua-aggre3-noc
+          - const: qcom,glymur-aggre3-noc
+      - items:
+          - enum:
+              - qcom,mahua-aggre4-noc
+          - const: qcom,glymur-aggre4-noc
+      - items:
+          - enum:
+              - qcom,mahua-mmss-noc
+          - const: qcom,glymur-mmss-noc
+      - items:
+          - enum:
+              - qcom,mahua-pcie-east-slv-noc
+          - const: qcom,glymur-pcie-east-slv-noc
+      - items:
+          - enum:
+              - qcom,mahua-lpass-lpiaon-noc
+          - const: qcom,glymur-lpass-lpiaon-noc
+      - items:
+          - enum:
+              - qcom,mahua-lpass-lpicx-noc
+          - const: qcom,glymur-lpass-lpicx-noc
+      - items:
+          - enum:
+              - qcom,mahua-lpass-ag-noc
+          - const: qcom,glymur-lpass-ag-noc
+      - items:
+          - enum:
+              - qcom,mahua-nsinoc
+          - const: qcom,glymur-nsinoc
+      - items:
+          - enum:
+              - qcom,mahua-oobm-ss-noc
+          - const: qcom,glymur-oobm-ss-noc
+      - items:
+          - enum:
+              - qcom,mahua-nsp-noc
+          - const: qcom,glymur-nsp-noc
+      - enum:
+          - qcom,glymur-aggre1-noc
+          - qcom,glymur-aggre2-noc
+          - qcom,glymur-aggre3-noc
+          - qcom,glymur-aggre4-noc
+          - qcom,glymur-clk-virt
+          - qcom,glymur-cnoc-cfg
+          - qcom,glymur-cnoc-main
+          - qcom,glymur-hscnoc
+          - qcom,glymur-lpass-ag-noc
+          - qcom,glymur-lpass-lpiaon-noc
+          - qcom,glymur-lpass-lpicx-noc
+          - qcom,glymur-mc-virt
+          - qcom,glymur-mmss-noc
+          - qcom,glymur-nsinoc
+          - qcom,glymur-nsp-noc
+          - qcom,glymur-oobm-ss-noc
+          - qcom,glymur-pcie-east-anoc
+          - qcom,glymur-pcie-east-slv-noc
+          - qcom,glymur-pcie-west-anoc
+          - qcom,glymur-pcie-west-slv-noc
+          - qcom,glymur-system-noc
+          - qcom,mahua-mc-virt
+          - qcom,mahua-cnoc-cfg
+          - qcom,mahua-pcie-west-anoc
+          - qcom,mahua-pcie-west-slv-noc
+          - qcom,mahua-hscnoc
 
   reg:
     maxItems: 1
@@ -63,6 +133,7 @@ allOf:
             enum:
               - qcom,glymur-clk-virt
               - qcom,glymur-mc-virt
+              - qcom,mahua-mc-virt
     then:
       properties:
         reg: false
@@ -85,6 +156,20 @@ allOf:
             - description: aggre PCIE_4 WEST AXI clock
             - description: aggre PCIE_6 WEST AXI clock
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,mahua-pcie-west-anoc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre PCIE_3B WEST AXI clock
+            - description: aggre PCIE_4 WEST AXI clock
+            - description: aggre PCIE_6 WEST AXI clock
+
   - if:
       properties:
         compatible:
@@ -132,6 +217,7 @@ allOf:
           contains:
             enum:
               - qcom,glymur-pcie-west-anoc
+              - qcom,mahua-pcie-west-anoc
               - qcom,glymur-pcie-east-anoc
               - qcom,glymur-aggre2-noc
               - qcom,glymur-aggre4-noc

-- 
2.43.0

[PATCH v2 2/2] interconnect: qcom: glymur: Add Mahua SoC support

[Raviteja Laggyshetty]

Mahua is a derivative of the Glymur SoC. Extend the
Glymur driver to support Mahua by:

  1. Adding new node definitions for interconnects that differ from Glymur
     (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
  2. Reusing existing Glymur definitions for identical NoCs.
  3. Overriding the channel and buswidth, with Mahua specific values for
     the differing NoCs

Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
 drivers/interconnect/qcom/glymur.c | 38 +++++++++++++++++++++++++++++++++-----
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom/glymur.c
index e5c07795a6c67ab8a59daf2fc4b8a5fa6dd014d6..cfe061c1a75a692c252c4a0d4ea63e71308223ba 100644
--- a/drivers/interconnect/qcom/glymur.c
+++ b/drivers/interconnect/qcom/glymur.c
@@ -9,6 +9,7 @@
 #include <linux/interconnect-provider.h>
 #include <linux/module.h>
 #include <linux/of_platform.h>
+#include <linux/property.h>
 #include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
 
 #include "bcm-voter.h"
@@ -1985,7 +1986,7 @@ static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
 	&bcm_cn1,
 };
 
-static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
+static struct qcom_icc_node *cnoc_cfg_nodes[] = {
 	[MASTER_CNOC_CFG] = &qsm_cfg,
 	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
 	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
@@ -2093,7 +2094,7 @@ static struct qcom_icc_bcm * const hscnoc_bcms[] = {
 	&bcm_sh1,
 };
 
-static struct qcom_icc_node * const hscnoc_nodes[] = {
+static struct qcom_icc_node *hscnoc_nodes[] = {
 	[MASTER_GPU_TCU] = &alm_gpu_tcu,
 	[MASTER_PCIE_TCU] = &alm_pcie_qtc,
 	[MASTER_SYS_TCU] = &alm_sys_tcu,
@@ -2377,7 +2378,7 @@ static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] = {
 	&bcm_sn6,
 };
 
-static struct qcom_icc_node * const pcie_west_anoc_nodes[] = {
+static struct qcom_icc_node *pcie_west_anoc_nodes[] = {
 	[MASTER_PCIE_WEST_ANOC_CFG] = &qsm_pcie_west_anoc_cfg,
 	[MASTER_PCIE_2] = &xm_pcie_2,
 	[MASTER_PCIE_3A] = &xm_pcie_3a,
@@ -2409,7 +2410,7 @@ static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] = {
 	&bcm_sn6,
 };
 
-static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] = {
+static struct qcom_icc_node *pcie_west_slv_noc_nodes[] = {
 	[MASTER_HSCNOC_PCIE_WEST] = &qnm_hscnoc_pcie_west,
 	[MASTER_CNOC_PCIE_WEST_SLAVE_CFG] = &qsm_cnoc_pcie_west_slave_cfg,
 	[SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] = &qhs_hscnoc_pcie_west_ms_mpu_cfg,
@@ -2470,6 +2471,28 @@ static const struct qcom_icc_desc glymur_system_noc = {
 	.num_bcms = ARRAY_SIZE(system_noc_bcms),
 };
 
+static int glymur_qnoc_probe(struct platform_device *pdev)
+{
+	if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
+		llcc_mc.channels = 8;
+		ebi.channels = 8;
+	} else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
+		qns_llcc.channels = 8;
+		chm_apps.channels = 4;
+		qnm_pcie_west.buswidth = 32;
+		hscnoc_nodes[MASTER_WLAN_Q6] = NULL;
+	} else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
+		qns_pcie_west_mem_noc.buswidth = 32;
+		pcie_west_anoc_nodes[MASTER_PCIE_3A] = NULL;
+	} else if (device_is_compatible(&pdev->dev, "qcom,mahua-cnoc-cfg")) {
+		cnoc_cfg_nodes[SLAVE_PCIE_3A_CFG] = NULL;
+	} else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-slv-noc")) {
+		pcie_west_slv_noc_nodes[SLAVE_PCIE_3A] = NULL;
+	}
+
+	return qcom_icc_rpmh_probe(pdev);
+}
+
 static const struct of_device_id qnoc_of_match[] = {
 	{ .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc},
 	{ .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc},
@@ -2477,12 +2500,15 @@ static const struct of_device_id qnoc_of_match[] = {
 	{ .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc},
 	{ .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt},
 	{ .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg},
+	{ .compatible = "qcom,mahua-cnoc-cfg", .data = &glymur_cnoc_cfg},
 	{ .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main},
 	{ .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc},
+	{ .compatible = "qcom,mahua-hscnoc", .data = &glymur_hscnoc},
 	{ .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc},
 	{ .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc},
 	{ .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc},
 	{ .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt},
+	{ .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt},
 	{ .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc},
 	{ .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc},
 	{ .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc},
@@ -2490,14 +2516,16 @@ static const struct of_device_id qnoc_of_match[] = {
 	{ .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc},
 	{ .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc},
 	{ .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
+	{ .compatible = "qcom,mahua-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
 	{ .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
+	{ .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
 	{ .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, qnoc_of_match);
 
 static struct platform_driver qnoc_driver = {
-	.probe = qcom_icc_rpmh_probe,
+	.probe = glymur_qnoc_probe,
 	.remove = qcom_icc_rpmh_remove,
 	.driver = {
 		.name = "qnoc-glymur",

-- 
2.43.0

Re: [PATCH v2 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC

[Konrad Dybcio]

On 1/27/26 4:22 AM, Raviteja Laggyshetty wrote:
> Document the RPMh Network-on-Chip (NoC) interconnect for the Qualcomm
> Mahua platform.
> 
> Mahua is a derivative of the Glymur SoC. Many interconnect nodes are
> identical and continue to use Glymur fallback compatibles. Mahua
> introduces SoC-specific configurations and topologies for several
> NoC blocks, including CNOC, HSCNOC, PCIe West ANoC/Slave NoCs.
> This updates the existing Glymur yaml schema to include Mahua-specific
> compatible strings, using two-cell "fallback" compatibles wherever
> the hardware is identical with Glymur.
> 
> Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> ---

Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 2/2] interconnect: qcom: glymur: Add Mahua SoC support

[Konrad Dybcio]

On 1/27/26 4:22 AM, Raviteja Laggyshetty wrote:
> Mahua is a derivative of the Glymur SoC. Extend the
> Glymur driver to support Mahua by:
> 
>   1. Adding new node definitions for interconnects that differ from Glymur
>      (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
>   2. Reusing existing Glymur definitions for identical NoCs.
>   3. Overriding the channel and buswidth, with Mahua specific values for
>      the differing NoCs
> 
> Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 2/2] interconnect: qcom: glymur: Add Mahua SoC support

[Konrad Dybcio]

On 1/27/26 4:22 AM, Raviteja Laggyshetty wrote:
> Mahua is a derivative of the Glymur SoC. Extend the
> Glymur driver to support Mahua by:
> 
>   1. Adding new node definitions for interconnects that differ from Glymur
>      (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
>   2. Reusing existing Glymur definitions for identical NoCs.
>   3. Overriding the channel and buswidth, with Mahua specific values for
>      the differing NoCs
> 
> Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 2/2] interconnect: qcom: glymur: Add Mahua SoC support

[Dmitry Baryshkov]

On Tue, Jan 27, 2026 at 03:22:07AM +0000, Raviteja Laggyshetty wrote:
> Mahua is a derivative of the Glymur SoC. Extend the
> Glymur driver to support Mahua by:
> 
>   1. Adding new node definitions for interconnects that differ from Glymur
>      (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
>   2. Reusing existing Glymur definitions for identical NoCs.
>   3. Overriding the channel and buswidth, with Mahua specific values for
>      the differing NoCs
> 
> Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> ---
>  drivers/interconnect/qcom/glymur.c | 38 +++++++++++++++++++++++++++++++++-----
>  1 file changed, 33 insertions(+), 5 deletions(-)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH v2 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC

[Krzysztof Kozlowski]

On Tue, Jan 27, 2026 at 03:22:06AM +0000, Raviteja Laggyshetty wrote:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - qcom,mahua-clk-virt
> +          - const: qcom,glymur-clk-virt
> +      - items:
> +          - enum:
> +              - qcom,mahua-cnoc-main
> +          - const: qcom,glymur-cnoc-main
> +      - items:
> +          - enum:
> +              - qcom,mahua-system-noc
> +          - const: qcom,glymur-system-noc
> +      - items:
> +          - enum:
> +              - qcom,mahua-pcie-east-anoc
> +          - const: qcom,glymur-pcie-east-anoc
> +      - items:
> +          - enum:
> +              - qcom,mahua-aggre1-noc
> +          - const: qcom,glymur-aggre1-noc

All these "items" blocks should be sorted by the fallback, so
qcom,glymur-aggre1-noc is before qcom,glymur-clk-virt.


> +      - items:
> +          - enum:
> +              - qcom,mahua-aggre2-noc
> +          - const: qcom,glymur-aggre2-noc
> +      - items:
> +          - enum:
> +              - qcom,mahua-aggre3-noc
> +          - const: qcom,glymur-aggre3-noc
> +      - items:
> +          - enum:
> +              - qcom,mahua-aggre4-noc
> +          - const: qcom,glymur-aggre4-noc
> +      - items:
> +          - enum:
> +              - qcom,mahua-mmss-noc
> +          - const: qcom,glymur-mmss-noc
> +      - items:
> +          - enum:
> +              - qcom,mahua-pcie-east-slv-noc
> +          - const: qcom,glymur-pcie-east-slv-noc
> +      - items:
> +          - enum:
> +              - qcom,mahua-lpass-lpiaon-noc
> +          - const: qcom,glymur-lpass-lpiaon-noc
> +      - items:
> +          - enum:
> +              - qcom,mahua-lpass-lpicx-noc
> +          - const: qcom,glymur-lpass-lpicx-noc
> +      - items:
> +          - enum:
> +              - qcom,mahua-lpass-ag-noc
> +          - const: qcom,glymur-lpass-ag-noc
> +      - items:
> +          - enum:
> +              - qcom,mahua-nsinoc
> +          - const: qcom,glymur-nsinoc
> +      - items:
> +          - enum:
> +              - qcom,mahua-oobm-ss-noc
> +          - const: qcom,glymur-oobm-ss-noc
> +      - items:
> +          - enum:
> +              - qcom,mahua-nsp-noc
> +          - const: qcom,glymur-nsp-noc
> +      - enum:
> +          - qcom,glymur-aggre1-noc
> +          - qcom,glymur-aggre2-noc
> +          - qcom,glymur-aggre3-noc
> +          - qcom,glymur-aggre4-noc
> +          - qcom,glymur-clk-virt
> +          - qcom,glymur-cnoc-cfg
> +          - qcom,glymur-cnoc-main
> +          - qcom,glymur-hscnoc
> +          - qcom,glymur-lpass-ag-noc
> +          - qcom,glymur-lpass-lpiaon-noc
> +          - qcom,glymur-lpass-lpicx-noc
> +          - qcom,glymur-mc-virt
> +          - qcom,glymur-mmss-noc
> +          - qcom,glymur-nsinoc
> +          - qcom,glymur-nsp-noc
> +          - qcom,glymur-oobm-ss-noc
> +          - qcom,glymur-pcie-east-anoc
> +          - qcom,glymur-pcie-east-slv-noc
> +          - qcom,glymur-pcie-west-anoc
> +          - qcom,glymur-pcie-west-slv-noc
> +          - qcom,glymur-system-noc
> +          - qcom,mahua-mc-virt
> +          - qcom,mahua-cnoc-cfg
> +          - qcom,mahua-pcie-west-anoc
> +          - qcom,mahua-pcie-west-slv-noc
> +          - qcom,mahua-hscnoc
>  
>    reg:
>      maxItems: 1
> @@ -63,6 +133,7 @@ allOf:
>              enum:
>                - qcom,glymur-clk-virt
>                - qcom,glymur-mc-virt
> +              - qcom,mahua-mc-virt
>      then:
>        properties:
>          reg: false
> @@ -85,6 +156,20 @@ allOf:
>              - description: aggre PCIE_4 WEST AXI clock
>              - description: aggre PCIE_6 WEST AXI clock
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,mahua-pcie-west-anoc
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: aggre PCIE_3B WEST AXI clock
> +            - description: aggre PCIE_4 WEST AXI clock
> +            - description: aggre PCIE_6 WEST AXI clock
> +
>    - if:
>        properties:
>          compatible:
> @@ -132,6 +217,7 @@ allOf:
>            contains:
>              enum:
>                - qcom,glymur-pcie-west-anoc
> +              - qcom,mahua-pcie-west-anoc

Messed sorting. I don't get why such trivialities are still happening...

>                - qcom,glymur-pcie-east-anoc
>                - qcom,glymur-aggre2-noc
>                - qcom,glymur-aggre4-noc
> 
> -- 
> 2.43.0
> 

Re: [PATCH v2 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC

[Raviteja Laggyshetty]

On 2/5/2026 5:25 PM, Krzysztof Kozlowski wrote:
> On Tue, Jan 27, 2026 at 03:22:06AM +0000, Raviteja Laggyshetty wrote:
>> +    oneOf:
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-clk-virt
>> +          - const: qcom,glymur-clk-virt
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-cnoc-main
>> +          - const: qcom,glymur-cnoc-main
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-system-noc
>> +          - const: qcom,glymur-system-noc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-pcie-east-anoc
>> +          - const: qcom,glymur-pcie-east-anoc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-aggre1-noc
>> +          - const: qcom,glymur-aggre1-noc
> 
> All these "items" blocks should be sorted by the fallback, so
> qcom,glymur-aggre1-noc is before qcom,glymur-clk-virt.

Will fix the sorting and post the next revision. 
> 
> 
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-aggre2-noc
>> +          - const: qcom,glymur-aggre2-noc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-aggre3-noc
>> +          - const: qcom,glymur-aggre3-noc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-aggre4-noc
>> +          - const: qcom,glymur-aggre4-noc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-mmss-noc
>> +          - const: qcom,glymur-mmss-noc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-pcie-east-slv-noc
>> +          - const: qcom,glymur-pcie-east-slv-noc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-lpass-lpiaon-noc
>> +          - const: qcom,glymur-lpass-lpiaon-noc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-lpass-lpicx-noc
>> +          - const: qcom,glymur-lpass-lpicx-noc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-lpass-ag-noc
>> +          - const: qcom,glymur-lpass-ag-noc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-nsinoc
>> +          - const: qcom,glymur-nsinoc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-oobm-ss-noc
>> +          - const: qcom,glymur-oobm-ss-noc
>> +      - items:
>> +          - enum:
>> +              - qcom,mahua-nsp-noc
>> +          - const: qcom,glymur-nsp-noc
>> +      - enum:
>> +          - qcom,glymur-aggre1-noc
>> +          - qcom,glymur-aggre2-noc
>> +          - qcom,glymur-aggre3-noc
>> +          - qcom,glymur-aggre4-noc
>> +          - qcom,glymur-clk-virt
>> +          - qcom,glymur-cnoc-cfg
>> +          - qcom,glymur-cnoc-main
>> +          - qcom,glymur-hscnoc
>> +          - qcom,glymur-lpass-ag-noc
>> +          - qcom,glymur-lpass-lpiaon-noc
>> +          - qcom,glymur-lpass-lpicx-noc
>> +          - qcom,glymur-mc-virt
>> +          - qcom,glymur-mmss-noc
>> +          - qcom,glymur-nsinoc
>> +          - qcom,glymur-nsp-noc
>> +          - qcom,glymur-oobm-ss-noc
>> +          - qcom,glymur-pcie-east-anoc
>> +          - qcom,glymur-pcie-east-slv-noc
>> +          - qcom,glymur-pcie-west-anoc
>> +          - qcom,glymur-pcie-west-slv-noc
>> +          - qcom,glymur-system-noc
>> +          - qcom,mahua-mc-virt
>> +          - qcom,mahua-cnoc-cfg
>> +          - qcom,mahua-pcie-west-anoc
>> +          - qcom,mahua-pcie-west-slv-noc
>> +          - qcom,mahua-hscnoc
>>  
>>    reg:
>>      maxItems: 1
>> @@ -63,6 +133,7 @@ allOf:
>>              enum:
>>                - qcom,glymur-clk-virt
>>                - qcom,glymur-mc-virt
>> +              - qcom,mahua-mc-virt
>>      then:
>>        properties:
>>          reg: false
>> @@ -85,6 +156,20 @@ allOf:
>>              - description: aggre PCIE_4 WEST AXI clock
>>              - description: aggre PCIE_6 WEST AXI clock
>>  
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - qcom,mahua-pcie-west-anoc
>> +    then:
>> +      properties:
>> +        clocks:
>> +          items:
>> +            - description: aggre PCIE_3B WEST AXI clock
>> +            - description: aggre PCIE_4 WEST AXI clock
>> +            - description: aggre PCIE_6 WEST AXI clock
>> +
>>    - if:
>>        properties:
>>          compatible:
>> @@ -132,6 +217,7 @@ allOf:
>>            contains:
>>              enum:
>>                - qcom,glymur-pcie-west-anoc
>> +              - qcom,mahua-pcie-west-anoc
> 
> Messed sorting. I don't get why such trivialities are still happening...
I will fix the sorting here as well and won't let this happen in future patches.
> 
>>                - qcom,glymur-pcie-east-anoc
>>                - qcom,glymur-aggre2-noc
>>                - qcom,glymur-aggre4-noc
>>
>> -- 
>> 2.43.0
>>