* [PATCH v5] irqchip/mmp: only touch the PJ4 & FIQ bits on enable/disable
@ 2019-01-28 15:59 Lubomir Rintel
2019-01-28 18:35 ` Marc Zyngier
0 siblings, 1 reply; 3+ messages in thread
From: Lubomir Rintel @ 2019-01-28 15:59 UTC (permalink / raw)
To: Marc Zyngier
Cc: Jason Cooper, Thomas Gleixner, linux-kernel, stable,
Lubomir Rintel, Pavel Machek
Resetting the bit 4 disables the interrupt delivery to the "secure
processor" core. This breaks the keyboard on a OLPC XO 1.75 laptop,
where the firmware running on the "secure processor" bit-bangs the
PS/2 protocol over the GPIO lines.
It is not clear what the rest of the bits are and Marvel was unhelpful
when asked for documentation. Aside from the SP bit, there are probably
priority bits.
Leaving the unknown bits as the firmware set them up seems to be a wiser
course of action compared to just turning them off.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Pavel Machek <pavel@ucw.cz>
---
Changes since v4:
- Remove unused ICU_INT_ROUTE_SP_IRQ define
- Try to further clarify the commit message
Changes since v3:
- Use #defined instead of integer literals
Changes since v2:
- Correct subsystem maintainers on Cc (irqchip)
Changes since v1:
- Adjusted wording & ack from Pavel
---
drivers/irqchip/irq-mmp.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
index 37a54797a137..fac8f1365f76 100644
--- a/drivers/irqchip/irq-mmp.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -34,6 +34,9 @@
#define SEL_INT_PENDING (1 << 6)
#define SEL_INT_NUM_MASK 0x3f
+#define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
+#define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
+
struct icu_chip_data {
int nr_irqs;
unsigned int virq_base;
@@ -190,7 +193,8 @@ static const struct mmp_intc_conf mmp_conf = {
static const struct mmp_intc_conf mmp2_conf = {
.conf_enable = 0x20,
.conf_disable = 0x0,
- .conf_mask = 0x7f,
+ .conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ |
+ MMP2_ICU_INT_ROUTE_PJ4_FIQ,
};
static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
--
2.20.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v5] irqchip/mmp: only touch the PJ4 & FIQ bits on enable/disable
2019-01-28 15:59 [PATCH v5] irqchip/mmp: only touch the PJ4 & FIQ bits on enable/disable Lubomir Rintel
@ 2019-01-28 18:35 ` Marc Zyngier
2019-01-28 18:41 ` Lubomir Rintel
0 siblings, 1 reply; 3+ messages in thread
From: Marc Zyngier @ 2019-01-28 18:35 UTC (permalink / raw)
To: Lubomir Rintel
Cc: Jason Cooper, Thomas Gleixner, linux-kernel, stable, Pavel Machek
I guess the subject is supposed to read: "only touch the PJ4 *IRQ* & FIQ
bits on enable/disable", right?
If that's the case, let me know, and I'll fix it up when applying it.
On 28/01/2019 15:59, Lubomir Rintel wrote:
> Resetting the bit 4 disables the interrupt delivery to the "secure
> processor" core. This breaks the keyboard on a OLPC XO 1.75 laptop,
> where the firmware running on the "secure processor" bit-bangs the
> PS/2 protocol over the GPIO lines.
>
> It is not clear what the rest of the bits are and Marvel was unhelpful
> when asked for documentation. Aside from the SP bit, there are probably
> priority bits.
>
> Leaving the unknown bits as the firmware set them up seems to be a wiser
> course of action compared to just turning them off.
>
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> Acked-by: Pavel Machek <pavel@ucw.cz>
>
> ---
> Changes since v4:
> - Remove unused ICU_INT_ROUTE_SP_IRQ define
> - Try to further clarify the commit message
>
> Changes since v3:
> - Use #defined instead of integer literals
>
> Changes since v2:
> - Correct subsystem maintainers on Cc (irqchip)
>
> Changes since v1:
> - Adjusted wording & ack from Pavel
> ---
> drivers/irqchip/irq-mmp.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
> index 37a54797a137..fac8f1365f76 100644
> --- a/drivers/irqchip/irq-mmp.c
> +++ b/drivers/irqchip/irq-mmp.c
> @@ -34,6 +34,9 @@
> #define SEL_INT_PENDING (1 << 6)
> #define SEL_INT_NUM_MASK 0x3f
>
> +#define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
> +#define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
> +
> struct icu_chip_data {
> int nr_irqs;
> unsigned int virq_base;
> @@ -190,7 +193,8 @@ static const struct mmp_intc_conf mmp_conf = {
> static const struct mmp_intc_conf mmp2_conf = {
> .conf_enable = 0x20,
> .conf_disable = 0x0,
> - .conf_mask = 0x7f,
> + .conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ |
> + MMP2_ICU_INT_ROUTE_PJ4_FIQ,
> };
>
> static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
>
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v5] irqchip/mmp: only touch the PJ4 & FIQ bits on enable/disable
2019-01-28 18:35 ` Marc Zyngier
@ 2019-01-28 18:41 ` Lubomir Rintel
0 siblings, 0 replies; 3+ messages in thread
From: Lubomir Rintel @ 2019-01-28 18:41 UTC (permalink / raw)
To: Marc Zyngier
Cc: Jason Cooper, Thomas Gleixner, linux-kernel, stable, Pavel Machek
On Mon, 2019-01-28 at 18:35 +0000, Marc Zyngier wrote:
> I guess the subject is supposed to read: "only touch the PJ4 *IRQ* & FIQ
> bits on enable/disable", right?
>
> If that's the case, let me know, and I'll fix it up when applying it.
Yes, that would make more sense.
Thank you
Lubo
> On 28/01/2019 15:59, Lubomir Rintel wrote:
> > Resetting the bit 4 disables the interrupt delivery to the "secure
> > processor" core. This breaks the keyboard on a OLPC XO 1.75 laptop,
> > where the firmware running on the "secure processor" bit-bangs the
> > PS/2 protocol over the GPIO lines.
> >
> > It is not clear what the rest of the bits are and Marvel was unhelpful
> > when asked for documentation. Aside from the SP bit, there are probably
> > priority bits.
> >
> > Leaving the unknown bits as the firmware set them up seems to be a wiser
> > course of action compared to just turning them off.
> >
> > Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> > Acked-by: Pavel Machek <pavel@ucw.cz>
> >
> > ---
> > Changes since v4:
> > - Remove unused ICU_INT_ROUTE_SP_IRQ define
> > - Try to further clarify the commit message
> >
> > Changes since v3:
> > - Use #defined instead of integer literals
> >
> > Changes since v2:
> > - Correct subsystem maintainers on Cc (irqchip)
> >
> > Changes since v1:
> > - Adjusted wording & ack from Pavel
> > ---
> > drivers/irqchip/irq-mmp.c | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
> > index 37a54797a137..fac8f1365f76 100644
> > --- a/drivers/irqchip/irq-mmp.c
> > +++ b/drivers/irqchip/irq-mmp.c
> > @@ -34,6 +34,9 @@
> > #define SEL_INT_PENDING (1 << 6)
> > #define SEL_INT_NUM_MASK 0x3f
> >
> > +#define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
> > +#define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
> > +
> > struct icu_chip_data {
> > int nr_irqs;
> > unsigned int virq_base;
> > @@ -190,7 +193,8 @@ static const struct mmp_intc_conf mmp_conf = {
> > static const struct mmp_intc_conf mmp2_conf = {
> > .conf_enable = 0x20,
> > .conf_disable = 0x0,
> > - .conf_mask = 0x7f,
> > + .conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ |
> > + MMP2_ICU_INT_ROUTE_PJ4_FIQ,
> > };
> >
> > static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
> >
>
> Thanks,
>
> M.
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-01-28 18:42 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-28 15:59 [PATCH v5] irqchip/mmp: only touch the PJ4 & FIQ bits on enable/disable Lubomir Rintel
2019-01-28 18:35 ` Marc Zyngier
2019-01-28 18:41 ` Lubomir Rintel
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®