Re: [PATCH v2 5/5] drm/msm/dpu: remove DSC feature bit for PINGPONG on SDM630

[Abhinav Kumar <quic_abhinavk@quicinc.com>]

On 3/1/2025 1:24 AM, Dmitry Baryshkov wrote:
> The SDM630 platform doesn't have DSC blocks nor does have it DSC
> registers in the PINGPONG block. Drop the DPU_PINGPONG_DSC feature bit
> from the PINGPONG's feature mask, replacing PINGPONG_SDM845_MASK with
> BIT(DPU_PINGPONG_DITHER).
> 
> Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platforms")
> Reported-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 
> ---
> Note, Konrad pointed out that vendor DT doesn't define DIPTHER support
> for this platform, however I believe this is because support for this
> platform predates DITHER support in the vendor kernels.
> ---

Yes this is correct. This chipset has dither support in ping-pong.

>   drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> index 3aed9aa4c533f167ece7b4a5eb84fe49c4929df5..99c0f824d8f00474812bde12e7d83ba3de1834f1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> @@ -115,14 +115,14 @@ static const struct dpu_pingpong_cfg sdm630_pp[] = {
>   	{
>   		.name = "pingpong_0", .id = PINGPONG_0,
>   		.base = 0x70000, .len = 0xd4,
> -		.features = PINGPONG_SDM845_MASK,
> +		.features = BIT(DPU_PINGPONG_DITHER),
>   		.sblk = &sdm845_pp_sblk,
>   		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>   		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
>   	}, {
>   		.name = "pingpong_2", .id = PINGPONG_2,
>   		.base = 0x71000, .len = 0xd4,
> -		.features = PINGPONG_SDM845_MASK,
> +		.features = BIT(DPU_PINGPONG_DITHER),
>   		.sblk = &sdm845_pp_sblk,
>   		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
>   		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
> 

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>