From: Atish Patra <atish.patra@wdc.com>
To: Christoph Hellwig <hch@infradead.org>,
Thomas Gleixner <tglx@linutronix.de>
Cc: "palmer@sifive.com" <palmer@sifive.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"robh@kernel.org" <robh@kernel.org>,
Damien Le Moal <Damien.LeMoal@wdc.com>,
"marc.zyngier@arm.com" <marc.zyngier@arm.com>,
"anup@brainfault.org" <anup@brainfault.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RFC 3/3] RISC-V: Remove per cpu clocksource
Date: Mon, 17 Sep 2018 11:32:31 -0700 [thread overview]
Message-ID: <c1773efc-d087-6dc2-0ba4-a71c8ae991be@wdc.com> (raw)
In-Reply-To: <20180917150149.GA25348@infradead.org>
On 9/17/18 8:01 AM, Christoph Hellwig wrote:
> On Mon, Sep 17, 2018 at 04:52:44PM +0200, Thomas Gleixner wrote:
>> If this really does not need configuration and all actual implementations
>> are not "allowed" to screw the timer up, then this surely can do without
>> DT.
>
> That would be the plan.
>
>>
>> Just for the record, this would be the first (architected) timer ever which
>> just works. I'm having a hard time to believe this, but I'd certainly
>> welcome it.
>
> And that would be the contact with reality. Note that the current
> scheme which just matches for the riscv hart (aka cpu core) nodes
> would not exactly help either.
>
I thought we will have a dedicated timer node (like all other arch)
sooner or later and we will just change TIMER_OF to match that node
instead of riscv hart.
In this way, we will not do something entirely different from any other
architecture.
Regards,
Atish
>>
>>> -TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
>>> +core_initcall(riscv_timer_init);
>>
>> Are you sure that core_initcall is not too late?
>
> No, I'm not at all. This is just intended as a quick throw-away draft.
>
prev parent reply other threads:[~2018-09-17 18:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-14 21:54 [RFC 0/3] Timer code cleanup Atish Patra
2018-09-14 21:54 ` [RFC 1/3] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
2018-09-17 14:20 ` Christoph Hellwig
2018-09-18 2:26 ` Atish Patra
2018-09-14 21:54 ` [RFC 2/3] RISC-V:Support per-hart timebase-frequency Atish Patra
2018-09-17 14:23 ` Christoph Hellwig
2018-09-18 2:23 ` Atish Patra
2018-09-29 0:20 ` Palmer Dabbelt
2018-09-14 21:54 ` [RFC 3/3] RISC-V: Remove per cpu clocksource Atish Patra
2018-09-17 14:35 ` Christoph Hellwig
2018-09-17 14:52 ` Thomas Gleixner
2018-09-17 15:01 ` Christoph Hellwig
2018-09-17 15:04 ` Thomas Gleixner
2018-09-17 15:54 ` Anup Patel
2018-09-17 18:32 ` Atish Patra [this message]
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