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From: Harry Wentland <hwentlan@amd.com>
To: YueHaibing <yuehaibing@huawei.com>,
	"Wentland, Harry" <Harry.Wentland@amd.com>,
	"Li, Sun peng (Leo)" <Sunpeng.Li@amd.com>,
	"Deucher, Alexander" <Alexander.Deucher@amd.com>,
	"Koenig, Christian" <Christian.Koenig@amd.com>,
	"Zhou, David(ChunMing)" <David1.Zhou@amd.com>,
	"airlied@linux.ie" <airlied@linux.ie>,
	"daniel@ffwll.ch" <daniel@ffwll.ch>, "Lei, Jun" <Jun.Lei@amd.com>,
	"Laktyushkin, Dmytro" <Dmytro.Laktyushkin@amd.com>,
	"Lakha, Bhawanpreet" <Bhawanpreet.Lakha@amd.com>,
	"Aberback, Joshua" <Joshua.Aberback@amd.com>,
	"Liu, Wenjing" <Wenjing.Liu@amd.com>,
	"Liu, Charlene" <Charlene.Liu@amd.com>,
	"Leung, Martin" <Martin.Leung@amd.com>
Cc: "amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH -next] drm/amdgpu/display: fix build error without CONFIG_DRM_AMD_DC_DSC_SUPPORT
Date: Mon, 26 Aug 2019 13:22:08 +0000	[thread overview]
Message-ID: <c324866d-855a-b259-4511-c69491a82c88@amd.com> (raw)
In-Reply-To: <20190826085707.12504-1-yuehaibing@huawei.com>



On 2019-08-26 4:57 a.m., YueHaibing wrote:
> If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails:
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct:
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28:
>  error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control?
>   dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
>                             ^~~~~~~~~~~~~~~~~~~~
>                             dcn20_dpp_pg_control
> 
> Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this.
> 
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot")
> Signed-off-by: YueHaibing <yuehaibing@huawei.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> index e146d1d..54d67f6 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> @@ -2092,7 +2092,11 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
>  	dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
>  	dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
>  	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>  	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
> +#else
> +	dc->hwss.dsc_pg_control = NULL;
> +#endif
>  	dc->hwss.disable_vga = dcn20_disable_vga;
>  
>  	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
> 

  reply	other threads:[~2019-08-26 13:22 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-26  8:57 YueHaibing
2019-08-26 13:22 ` Harry Wentland [this message]
2019-08-26 15:18   ` Alex Deucher

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