[PATCH -next] drm/amdgpu/display: fix build error without CONFIG_DRM_AMD_DC_DSC_SUPPORT

[PATCH -next] drm/amdgpu/display: fix build error without CONFIG_DRM_AMD_DC_DSC_SUPPORT

[YueHaibing]

If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28:
 error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control?
  dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
                            ^~~~~~~~~~~~~~~~~~~~
                            dcn20_dpp_pg_control

Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this.

Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index e146d1d..54d67f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2092,7 +2092,11 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
 	dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
 	dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
 	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
+#else
+	dc->hwss.dsc_pg_control = NULL;
+#endif
 	dc->hwss.disable_vga = dcn20_disable_vga;
 
 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-- 
2.7.4

Re: [PATCH -next] drm/amdgpu/display: fix build error without CONFIG_DRM_AMD_DC_DSC_SUPPORT

[Harry Wentland]

On 2019-08-26 4:57 a.m., YueHaibing wrote:
> If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails:
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct:
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28:
>  error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control?
>   dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
>                             ^~~~~~~~~~~~~~~~~~~~
>                             dcn20_dpp_pg_control
> 
> Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this.
> 
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot")
> Signed-off-by: YueHaibing <yuehaibing@huawei.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> index e146d1d..54d67f6 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> @@ -2092,7 +2092,11 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
>  	dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
>  	dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
>  	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>  	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
> +#else
> +	dc->hwss.dsc_pg_control = NULL;
> +#endif
>  	dc->hwss.disable_vga = dcn20_disable_vga;
>  
>  	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
> 

Re: [PATCH -next] drm/amdgpu/display: fix build error without CONFIG_DRM_AMD_DC_DSC_SUPPORT

[Alex Deucher]

On Mon, Aug 26, 2019 at 9:22 AM Harry Wentland <hwentlan@amd.com> wrote:
>
>
>
> On 2019-08-26 4:57 a.m., YueHaibing wrote:
> > If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct:
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28:
> >  error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control?
> >   dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
> >                             ^~~~~~~~~~~~~~~~~~~~
> >                             dcn20_dpp_pg_control
> >
> > Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this.
> >
> > Reported-by: Hulk Robot <hulkci@huawei.com>
> > Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot")
> > Signed-off-by: YueHaibing <yuehaibing@huawei.com>
>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
>

Applied.  Thanks,

Alex

> Harry
>
> > ---
> >  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > index e146d1d..54d67f6 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > @@ -2092,7 +2092,11 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
> >       dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
> >       dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
> >       dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
> > +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> >       dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
> > +#else
> > +     dc->hwss.dsc_pg_control = NULL;
> > +#endif
> >       dc->hwss.disable_vga = dcn20_disable_vga;
> >
> >       if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
> >
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