[PATCH v2 0/2] Enable AONMIX MQS for IMX95-15x15-FRDM board

[PATCH v2 0/2] Enable AONMIX MQS for IMX95-15x15-FRDM board

[Laurentiu Mihalcea]

From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

This series enables AONMIX MQS (i.e. MQS1) for the IMX95-15x15-FRDM board.

---
Changes in v2:
- adjust binding commit message as suggested by Frank
- replace whitespaces with tabs in MQS pinctrl definition
- link to v1: https://lore.kernel.org/lkml/20260120150329.1486-1-laurentiumihalcea111@gmail.com/
---

Laurentiu Mihalcea (2):
  ASoC: dt-bindings: fsl,mqs: make gpr optional for SM-based SoCs
  arm64: dts: imx95-15x15-frdm: support AONMIX MQS

 .../devicetree/bindings/sound/fsl,mqs.yaml    | 12 ++-
 .../boot/dts/freescale/imx95-15x15-frdm.dts   | 73 +++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx95.dtsi      |  5 ++
 3 files changed, 88 insertions(+), 2 deletions(-)

-- 
2.43.0

[PATCH v2 1/2] ASoC: dt-bindings: fsl,mqs: make gpr optional for SM-based SoCs

[Laurentiu Mihalcea]

From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

For SM-based SoCs (i.e. MX95, MX943), GPR configuration is performed by
the SM coprocessor. Thus, GPR is transparent to the software and does not
need to be described in the devicetree. Make it optional.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
---
 Documentation/devicetree/bindings/sound/fsl,mqs.yaml | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/fsl,mqs.yaml b/Documentation/devicetree/bindings/sound/fsl,mqs.yaml
index 1415247c92c8..bcc265a742c7 100644
--- a/Documentation/devicetree/bindings/sound/fsl,mqs.yaml
+++ b/Documentation/devicetree/bindings/sound/fsl,mqs.yaml
@@ -63,6 +63,16 @@ required:
 
 allOf:
   - $ref: dai-common.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - fsl,imx6sx-mqs
+              - fsl,imx93-mqs
+    then:
+      required:
+        - gpr
   - if:
       properties:
         compatible:
@@ -91,8 +101,6 @@ allOf:
         clock-names:
           items:
             - const: mclk
-      required:
-        - gpr
 
 unevaluatedProperties: false
 
-- 
2.43.0

[PATCH v2 2/2] arm64: dts: imx95-15x15-frdm: support AONMIX MQS

[Laurentiu Mihalcea]

From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

Add support for AONMIX MQS (i.e. MQS1).

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
---
 .../boot/dts/freescale/imx95-15x15-frdm.dts   | 73 +++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx95.dtsi      |  5 ++
 2 files changed, 78 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
index ca1c4966c867..0f43e3be7058 100644
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
@@ -243,6 +243,12 @@ codec {
 		};
 	};
 
+	sound-mqs {
+		compatible = "audio-graph-card2";
+		links = <&sai1_port1>;
+		label = "mqs-audio";
+	};
+
 	usdhc3_pwrseq: usdhc3-pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>;
@@ -473,6 +479,21 @@ &mu7 {
 	status = "okay";
 };
 
+&mqs1 {
+	clocks = <&scmi_clk IMX95_CLK_SAI1>;
+	clock-names = "mclk";
+	pinctrl-0 = <&pinctrl_mqs1>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	mqs1_port: port {
+		mqs1_ep: endpoint {
+			dai-format = "left_j";
+			remote-endpoint = <&sai1_port1_ep>;
+		};
+	};
+};
+
 &netc_blk_ctrl {
 	status = "okay";
 };
@@ -534,6 +555,51 @@ &pcie0 {
 	status = "okay";
 };
 
+&sai1 {
+	clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>,
+		 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>,
+		 <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+		 <&scmi_clk IMX95_CLK_AUDIOPLL2>;
+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
+	assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+			  <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+			  <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+			  <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+			  <&scmi_clk IMX95_CLK_SAI1>;
+	assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>;
+	assigned-clock-rates = <3932160000>, <3612672000>,
+			       <393216000>, <361267200>,
+			       <24576000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* leave unconnected - no RX in the context of MQS */
+		port@0 {
+			reg = <0>;
+
+			endpoint {
+			};
+		};
+
+		sai1_port1: port@1 {
+			reg = <1>;
+			mclk-fs = <512>;
+
+			sai1_port1_ep: endpoint {
+				dai-format = "left_j";
+				system-clock-direction-out;
+				bitclock-master;
+				frame-master;
+				remote-endpoint = <&mqs1_ep>;
+			};
+		};
+	};
+};
+
 &scmi_iomuxc {
 	pinctrl_emdio: emdiogrp {
 		fsl,pins = <
@@ -618,6 +684,13 @@ IMX95_PAD_GPIO_IO31__LPI2C4_SCL				0x40000b9e
 		>;
 	};
 
+	pinctrl_mqs1: mqs1grp {
+		fsl,pins = <
+			IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT		0x31e
+			IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT		0x31e
+		>;
+	};
+
 	pinctrl_pcal6524: pcal6524grp {
 		fsl,pins = <
 			IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14			0x31e
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 55e2da094c88..0c55861d673c 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -391,6 +391,11 @@ scmi_misc: protocol@84 {
 		};
 	};
 
+	mqs1: mqs-1 {
+		compatible = "fsl,imx95-aonmix-mqs";
+		status = "disabled";
+	};
+
 	pmu {
 		compatible = "arm,cortex-a55-pmu";
 		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
-- 
2.43.0

Re: [PATCH v2 2/2] arm64: dts: imx95-15x15-frdm: support AONMIX MQS

[Daniel Baluta]

On Mon, Jan 26, 2026 at 4:57 PM Laurentiu Mihalcea
<laurentiumihalcea111@gmail.com> wrote:
>
> From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
>
> Add support for AONMIX MQS (i.e. MQS1).
>
> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>

Re: [PATCH v2 2/2] arm64: dts: imx95-15x15-frdm: support AONMIX MQS

[Frank Li]

On Mon, Jan 26, 2026 at 06:55:37AM -0800, Laurentiu Mihalcea wrote:
> From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
>
> Add support for AONMIX MQS (i.e. MQS1).
>
> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
> ---
>  .../boot/dts/freescale/imx95-15x15-frdm.dts   | 73 +++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx95.dtsi      |  5 ++

Chip's dtsi and board dts should be two patches.

Frank
>  2 files changed, 78 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> index ca1c4966c867..0f43e3be7058 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> @@ -243,6 +243,12 @@ codec {
>  		};
>  	};
>
> +	sound-mqs {
> +		compatible = "audio-graph-card2";
> +		links = <&sai1_port1>;
> +		label = "mqs-audio";
> +	};
> +
>  	usdhc3_pwrseq: usdhc3-pwrseq {
>  		compatible = "mmc-pwrseq-simple";
>  		reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>;
> @@ -473,6 +479,21 @@ &mu7 {
>  	status = "okay";
>  };
>
> +&mqs1 {
> +	clocks = <&scmi_clk IMX95_CLK_SAI1>;
> +	clock-names = "mclk";
> +	pinctrl-0 = <&pinctrl_mqs1>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +
> +	mqs1_port: port {
> +		mqs1_ep: endpoint {
> +			dai-format = "left_j";
> +			remote-endpoint = <&sai1_port1_ep>;
> +		};
> +	};
> +};
> +
>  &netc_blk_ctrl {
>  	status = "okay";
>  };
> @@ -534,6 +555,51 @@ &pcie0 {
>  	status = "okay";
>  };
>
> +&sai1 {
> +	clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>,
> +		 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>,
> +		 <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>,
> +		 <&scmi_clk IMX95_CLK_AUDIOPLL2>;
> +	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
> +	assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
> +			  <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
> +			  <&scmi_clk IMX95_CLK_AUDIOPLL1>,
> +			  <&scmi_clk IMX95_CLK_AUDIOPLL2>,
> +			  <&scmi_clk IMX95_CLK_SAI1>;
> +	assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>;
> +	assigned-clock-rates = <3932160000>, <3612672000>,
> +			       <393216000>, <361267200>,
> +			       <24576000>;
> +	fsl,sai-mclk-direction-output;
> +	status = "okay";
> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		/* leave unconnected - no RX in the context of MQS */
> +		port@0 {
> +			reg = <0>;
> +
> +			endpoint {
> +			};
> +		};
> +
> +		sai1_port1: port@1 {
> +			reg = <1>;
> +			mclk-fs = <512>;
> +
> +			sai1_port1_ep: endpoint {
> +				dai-format = "left_j";
> +				system-clock-direction-out;
> +				bitclock-master;
> +				frame-master;
> +				remote-endpoint = <&mqs1_ep>;
> +			};
> +		};
> +	};
> +};
> +
>  &scmi_iomuxc {
>  	pinctrl_emdio: emdiogrp {
>  		fsl,pins = <
> @@ -618,6 +684,13 @@ IMX95_PAD_GPIO_IO31__LPI2C4_SCL				0x40000b9e
>  		>;
>  	};
>
> +	pinctrl_mqs1: mqs1grp {
> +		fsl,pins = <
> +			IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT		0x31e
> +			IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT		0x31e
> +		>;
> +	};
> +
>  	pinctrl_pcal6524: pcal6524grp {
>  		fsl,pins = <
>  			IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14			0x31e
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 55e2da094c88..0c55861d673c 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -391,6 +391,11 @@ scmi_misc: protocol@84 {
>  		};
>  	};
>
> +	mqs1: mqs-1 {
> +		compatible = "fsl,imx95-aonmix-mqs";
> +		status = "disabled";
> +	};
> +
>  	pmu {
>  		compatible = "arm,cortex-a55-pmu";
>  		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> --
> 2.43.0
>

RE: [EXT] [PATCH v2 2/2] arm64: dts: imx95-15x15-frdm: support AONMIX MQS

[Chancel Liu]

> From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
> 
> Add support for AONMIX MQS (i.e. MQS1).
> 
> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

Reviewed-by: Chancel Liu <chancel.liu@nxp.com>

Regards, 
Chancel Liu

> ---
>  .../boot/dts/freescale/imx95-15x15-frdm.dts   | 73 +++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx95.dtsi      |  5 ++
>  2 files changed, 78 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> index ca1c4966c867..0f43e3be7058 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
> @@ -243,6 +243,12 @@ codec {
>                 };
>         };
> 
> +       sound-mqs {
> +               compatible = "audio-graph-card2";
> +               links = <&sai1_port1>;
> +               label = "mqs-audio";
> +       };
> +
>         usdhc3_pwrseq: usdhc3-pwrseq {
>                 compatible = "mmc-pwrseq-simple";
>                 reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>; @@ -473,6 +479,21
> @@ &mu7 {
>         status = "okay";
>  };
> 
> +&mqs1 {
> +       clocks = <&scmi_clk IMX95_CLK_SAI1>;
> +       clock-names = "mclk";
> +       pinctrl-0 = <&pinctrl_mqs1>;
> +       pinctrl-names = "default";
> +       status = "okay";
> +
> +       mqs1_port: port {
> +               mqs1_ep: endpoint {
> +                       dai-format = "left_j";
> +                       remote-endpoint = <&sai1_port1_ep>;
> +               };
> +       };
> +};
> +
>  &netc_blk_ctrl {
>         status = "okay";
>  };
> @@ -534,6 +555,51 @@ &pcie0 {
>         status = "okay";
>  };
> 
> +&sai1 {
> +       clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>,
> +                <&scmi_clk IMX95_CLK_SAI1>, <&dummy>,
> +                <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>,
> +                <&scmi_clk IMX95_CLK_AUDIOPLL2>;
> +       clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
> +       assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
> +                         <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
> +                         <&scmi_clk IMX95_CLK_AUDIOPLL1>,
> +                         <&scmi_clk IMX95_CLK_AUDIOPLL2>,
> +                         <&scmi_clk IMX95_CLK_SAI1>;
> +       assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk
> IMX95_CLK_AUDIOPLL1>;
> +       assigned-clock-rates = <3932160000>, <3612672000>,
> +                              <393216000>, <361267200>,
> +                              <24576000>;
> +       fsl,sai-mclk-direction-output;
> +       status = "okay";
> +
> +       ports {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               /* leave unconnected - no RX in the context of MQS */
> +               port@0 {
> +                       reg = <0>;
> +
> +                       endpoint {
> +                       };
> +               };
> +
> +               sai1_port1: port@1 {
> +                       reg = <1>;
> +                       mclk-fs = <512>;
> +
> +                       sai1_port1_ep: endpoint {
> +                               dai-format = "left_j";
> +                               system-clock-direction-out;
> +                               bitclock-master;
> +                               frame-master;
> +                               remote-endpoint = <&mqs1_ep>;
> +                       };
> +               };
> +       };
> +};
> +
>  &scmi_iomuxc {
>         pinctrl_emdio: emdiogrp {
>                 fsl,pins = <
> @@ -618,6 +684,13 @@ IMX95_PAD_GPIO_IO31__LPI2C4_SCL
> 0x40000b9e
>                 >;
>         };
> 
> +       pinctrl_mqs1: mqs1grp {
> +               fsl,pins = <
> +                       IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT
> 0x31e
> +                       IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT
> 0x31e
> +               >;
> +       };
> +
>         pinctrl_pcal6524: pcal6524grp {
>                 fsl,pins = <
>                         IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14                     0x31e
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi
> b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 55e2da094c88..0c55861d673c 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -391,6 +391,11 @@ scmi_misc: protocol@84 {
>                 };
>         };
> 
> +       mqs1: mqs-1 {
> +               compatible = "fsl,imx95-aonmix-mqs";
> +               status = "disabled";
> +       };
> +
>         pmu {
>                 compatible = "arm,cortex-a55-pmu";
>                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_HIGH)>;
> --
> 2.43.0

Re: (subset) [PATCH v2 0/2] Enable AONMIX MQS for IMX95-15x15-FRDM board

[Mark Brown]

On Mon, 26 Jan 2026 06:55:35 -0800, Laurentiu Mihalcea wrote:
> This series enables AONMIX MQS (i.e. MQS1) for the IMX95-15x15-FRDM board.
> 

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/2] ASoC: dt-bindings: fsl,mqs: make gpr optional for SM-based SoCs
      commit: f80bee70b1938f904d0b12783044d5eebcc6879b

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Re: [PATCH v2 2/2] arm64: dts: imx95-15x15-frdm: support AONMIX MQS

[Laurentiu Mihalcea]

On 1/26/2026 8:40 AM, Frank Li wrote:
> On Mon, Jan 26, 2026 at 06:55:37AM -0800, Laurentiu Mihalcea wrote:
>> From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
>>
>> Add support for AONMIX MQS (i.e. MQS1).
>>
>> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
>> ---
>>  .../boot/dts/freescale/imx95-15x15-frdm.dts   | 73 +++++++++++++++++++
>>  arch/arm64/boot/dts/freescale/imx95.dtsi      |  5 ++
> Chip's dtsi and board dts should be two patches.
>
> Frank


What's the rationale for this? Is this "rule" documented anywhere?

IMO, the DTSI-related changes are small enough that it doesn't justify

the split into different patches. The split would've made more sense

if we were touching more than 1 board.

Re: [PATCH v2 2/2] arm64: dts: imx95-15x15-frdm: support AONMIX MQS

[Frank Li]

On Tue, Jan 27, 2026 at 04:22:19AM -0800, Laurentiu Mihalcea wrote:
>
> On 1/26/2026 8:40 AM, Frank Li wrote:
> > On Mon, Jan 26, 2026 at 06:55:37AM -0800, Laurentiu Mihalcea wrote:
> >> From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
> >>
> >> Add support for AONMIX MQS (i.e. MQS1).
> >>
> >> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
> >> ---
> >>  .../boot/dts/freescale/imx95-15x15-frdm.dts   | 73 +++++++++++++++++++
> >>  arch/arm64/boot/dts/freescale/imx95.dtsi      |  5 ++
> > Chip's dtsi and board dts should be two patches.
> >
> > Frank
>
>
> What's the rationale for this? Is this "rule" documented anywhere?
>
> IMO, the DTSI-related changes are small enough that it doesn't justify
>
> the split into different patches. The split would've made more sense
>
> if we were touching more than 1 board.

Shawn's reqirement. I want to continue to follow this rule.

Frank

>