* [RESEND PATCH V4 0/3] riscv: mm: Add soft-dirty and uffd-wp support
@ 2024-08-30 1:10 Chunyan Zhang
2024-08-30 1:10 ` [RESEND PATCH V4 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9) Chunyan Zhang
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Chunyan Zhang @ 2024-08-30 1:10 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Andrew Morton, Alexandre Ghiti
Cc: linux-riscv, linux-kernel, Chunyan Zhang
This patchset adds soft dirty and userfaultfd write protect tracking support
for RISC-V.
As described in the patches, we are trying to utilize only one free PTE
bit(9) to support three kernel features (devmap, soft-dirty, uffd-wp).
Users cannot have them supported at the same time (have to select
one when building the kernel).
This patchset has been tested with:
1) The kselftest mm suite in which soft-dirty, madv_populate, test_unmerge_uffd_wp,
and uffd-unit-tests run and pass, and no regressions are observed in any of the
other tests.
2) CRIU:
- 'criu check --feature mem_dirty_track' returns supported;
- incremental_dumps[1] and simple_loop [2] dump and restores work fine;
- zdtm test suite can run under host mode.
This patchset applies on top of v6.11-rc1.
V4:
- Added bit(4) descriptions into "Format of swap PTE".
V3:
- Fixed the issue reported by kernel test irobot <lkp@intel.com>.
V1 -> V2:
- Add uffd-wp supported;
- Make soft-dirty uffd-wp and devmap mutually exclusive which all use the same PTE bit;
- Add test results of CRIU in the cover-letter.
[1] https://www.criu.org/Incremental_dumps
[2] https://asciinema.org/a/232445
Chunyan Zhang (3):
riscv: mm: Prepare for reusing PTE RSW bit(9)
riscv: mm: Add soft-dirty page tracking support
riscv: mm: Add uffd write-protect support
arch/riscv/Kconfig | 34 ++++++-
arch/riscv/include/asm/pgtable-64.h | 2 +-
arch/riscv/include/asm/pgtable-bits.h | 31 ++++++
arch/riscv/include/asm/pgtable.h | 133 +++++++++++++++++++++++++-
4 files changed, 197 insertions(+), 3 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RESEND PATCH V4 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9)
2024-08-30 1:10 [RESEND PATCH V4 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
@ 2024-08-30 1:10 ` Chunyan Zhang
2024-11-05 12:45 ` Alexandre Ghiti
2024-08-30 1:11 ` [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support Chunyan Zhang
2024-08-30 1:11 ` [RESEND PATCH V4 3/3] riscv: mm: Add uffd write-protect support Chunyan Zhang
2 siblings, 1 reply; 15+ messages in thread
From: Chunyan Zhang @ 2024-08-30 1:10 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Andrew Morton, Alexandre Ghiti
Cc: linux-riscv, linux-kernel, Chunyan Zhang
The PTE bit(9) on RISC-V is reserved for software, it is used by DEVMAP
now which has to be disabled if we want to use bit(9) for other features,
since there's no more free PTE bit on RISC-V now.
So to make ARCH_HAS_PTE_DEVMAP selectable, this patch uses it as
the build condition of devmap definitions.
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
arch/riscv/include/asm/pgtable-64.h | 2 +-
arch/riscv/include/asm/pgtable-bits.h | 6 ++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 0897dd99ab8d..babb8d2b0f0b 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -398,7 +398,7 @@ static inline struct page *pgd_page(pgd_t pgd)
#define p4d_offset p4d_offset
p4d_t *p4d_offset(pgd_t *pgd, unsigned long address);
-#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && defined(CONFIG_ARCH_HAS_PTE_DEVMAP)
static inline int pte_devmap(pte_t pte);
static inline pte_t pmd_pte(pmd_t pmd);
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index a8f5205cea54..5bcc73430829 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -19,7 +19,13 @@
#define _PAGE_SOFT (3 << 8) /* Reserved for software */
#define _PAGE_SPECIAL (1 << 8) /* RSW: 0x1 */
+
+#ifdef CONFIG_ARCH_HAS_PTE_DEVMAP
#define _PAGE_DEVMAP (1 << 9) /* RSW, devmap */
+#else
+#define _PAGE_DEVMAP 0
+#endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
+
#define _PAGE_TABLE _PAGE_PRESENT
/*
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support
2024-08-30 1:10 [RESEND PATCH V4 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
2024-08-30 1:10 ` [RESEND PATCH V4 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9) Chunyan Zhang
@ 2024-08-30 1:11 ` Chunyan Zhang
2024-08-30 1:31 ` Jinjie Ruan
2024-11-05 13:13 ` Alexandre Ghiti
2024-08-30 1:11 ` [RESEND PATCH V4 3/3] riscv: mm: Add uffd write-protect support Chunyan Zhang
2 siblings, 2 replies; 15+ messages in thread
From: Chunyan Zhang @ 2024-08-30 1:11 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Andrew Morton, Alexandre Ghiti
Cc: linux-riscv, linux-kernel, Chunyan Zhang
The PTE bit(9) is reserved for software, now used by DEVMAP,
this patch reuse bit(9) for soft-dirty which is enabled only
if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
and devmap will be mutually exclusive on RISC-V.
To add swap PTE soft-dirty tracking, we borrow bit (4) which is
available for swap PTEs on RISC-V systems.
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
arch/riscv/Kconfig | 27 ++++++++++-
arch/riscv/include/asm/pgtable-bits.h | 12 +++++
arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
3 files changed, 106 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0f3cd7c3a436..f1460fc01cd4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -39,7 +39,6 @@ config RISCV
select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
select ARCH_HAS_PMEM_API
select ARCH_HAS_PREPARE_SYNC_CORE_CMD
- select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
select ARCH_HAS_PTE_SPECIAL
select ARCH_HAS_SET_DIRECT_MAP if MMU
select ARCH_HAS_SET_MEMORY if MMU
@@ -948,6 +947,32 @@ config RANDOMIZE_BASE
If unsure, say N.
+choice
+ prompt "PET RSW Bit(9) used for"
+ default RISCV_HAS_PTE_DEVMEP
+ depends on MMU && 64BIT
+ help
+ RISC-V PTE bit(9) is reserved for software, and used by more than
+ one kernel features which cannot be supported at the same time.
+ So we have to select one for it.
+
+config RISCV_HAS_PTE_DEVMEP
+ bool "DEVMAP mark"
+ select ARCH_HAS_PTE_DEVMAP
+ help
+ The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
+ PTEs support to function.
+
+ So if you want to use ZONE_DEVICE, select this.
+
+config RISCV_HAS_SOFT_DIRTY
+ bool "soft dirty"
+ select HAVE_ARCH_SOFT_DIRTY
+ help
+ The PTE bit(9) is used for soft-dirty tracking.
+
+endchoice
+
endmenu # "Kernel features"
menu "Boot options"
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index 5bcc73430829..c6d51fe9fc6f 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -26,6 +26,18 @@
#define _PAGE_DEVMAP 0
#endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
+#ifdef CONFIG_MEM_SOFT_DIRTY
+#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
+/*
+ * BIT 4 is not involved into swap entry computation, so we
+ * can borrow it for swap page soft-dirty tracking.
+ */
+#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
+#else
+#define _PAGE_SOFT_DIRTY 0
+#define _PAGE_SWP_SOFT_DIRTY 0
+#endif /* CONFIG_MEM_SOFT_DIRTY */
+
#define _PAGE_TABLE _PAGE_PRESENT
/*
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 089f3c9f56a3..d41507919ef2 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
static inline pte_t pte_mkdirty(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_DIRTY);
+ return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
}
static inline pte_t pte_mkclean(pte_t pte)
@@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
return pte;
}
+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
+static inline int pte_soft_dirty(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_SOFT_DIRTY;
+}
+
+static inline pte_t pte_mksoft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
+}
+
+static inline pte_t pte_clear_soft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
+}
+
+static inline int pte_swp_soft_dirty(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
+}
+
+static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
+}
+
+static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
+}
+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
+
#ifdef CONFIG_RISCV_ISA_SVNAPOT
#define pte_leaf_size(pte) (pte_napot(pte) ? \
napot_cont_size(napot_cont_order(pte)) :\
@@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
}
+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
+static inline int pmd_soft_dirty(pmd_t pmd)
+{
+ return pte_soft_dirty(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
+}
+
+#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
+static inline int pmd_swp_soft_dirty(pmd_t pmd)
+{
+ return pte_swp_soft_dirty(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
+}
+#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
+
static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
pmd_t *pmdp, pmd_t pmd)
{
@@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
* Format of swap PTE:
* bit 0: _PAGE_PRESENT (zero)
* bit 1 to 3: _PAGE_LEAF (zero)
+ * bit 4: _PAGE_SWP_SOFT_DIRTY
* bit 5: _PAGE_PROT_NONE (zero)
* bit 6: exclusive marker
* bits 7 to 11: swap type
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RESEND PATCH V4 3/3] riscv: mm: Add uffd write-protect support
2024-08-30 1:10 [RESEND PATCH V4 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
2024-08-30 1:10 ` [RESEND PATCH V4 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9) Chunyan Zhang
2024-08-30 1:11 ` [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support Chunyan Zhang
@ 2024-08-30 1:11 ` Chunyan Zhang
2024-08-30 1:34 ` Jinjie Ruan
2024-11-05 13:24 ` Alexandre Ghiti
2 siblings, 2 replies; 15+ messages in thread
From: Chunyan Zhang @ 2024-08-30 1:11 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Andrew Morton, Alexandre Ghiti
Cc: linux-riscv, linux-kernel, Chunyan Zhang
Reuse PTE bit(9) to do uffd-wp tracking and make it mutually exclusive
with soft-dirty and DEVMAP which all use this PTE bit.
Additionally for tracking the uffd-wp state as a PTE swap bit,
we use swap entry pte bit(4) which is also used by swap
soft-dirty tracking.
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
arch/riscv/Kconfig | 7 +++
arch/riscv/include/asm/pgtable-bits.h | 13 ++++++
arch/riscv/include/asm/pgtable.h | 66 ++++++++++++++++++++++++++-
3 files changed, 85 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f1460fc01cd4..aa595a5ed4b8 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -971,6 +971,13 @@ config RISCV_HAS_SOFT_DIRTY
help
The PTE bit(9) is used for soft-dirty tracking.
+config RISCV_HAS_USERFAULTFD_WP
+ bool "userfaultfd write protection"
+ select HAVE_ARCH_USERFAULTFD_WP
+ depends on USERFAULTFD
+ help
+ The PTE bit(9) is used for userfaultfd write-protected
+ tracking.
endchoice
endmenu # "Kernel features"
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index c6d51fe9fc6f..7de16141c049 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -38,6 +38,19 @@
#define _PAGE_SWP_SOFT_DIRTY 0
#endif /* CONFIG_MEM_SOFT_DIRTY */
+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
+/*
+ * CONFIG_HAVE_ARCH_USERFAULTFD_WP is mutually exclusive with
+ * HAVE_ARCH_SOFT_DIRTY so we can use the same bit for uffd-wp
+ * and soft-dirty tracking.
+ */
+#define _PAGE_UFFD_WP (1 << 9) /* RSW: 0x2 for uffd-wp tracking */
+#define _PAGE_SWP_UFFD_WP _PAGE_USER
+#else
+#define _PAGE_UFFD_WP 0
+#define _PAGE_SWP_UFFD_WP 0
+#endif
+
#define _PAGE_TABLE _PAGE_PRESENT
/*
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index d41507919ef2..6ce4c9ba862a 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -417,6 +417,38 @@ static inline pte_t pte_wrprotect(pte_t pte)
return __pte(pte_val(pte) & ~(_PAGE_WRITE));
}
+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
+static inline int pte_uffd_wp(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_UFFD_WP;
+}
+
+static inline pte_t pte_mkuffd_wp(pte_t pte)
+{
+ return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD_WP));
+}
+
+static inline pte_t pte_clear_uffd_wp(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_UFFD_WP));
+}
+
+static inline int pte_swp_uffd_wp(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_SWP_UFFD_WP;
+}
+
+static inline pte_t pte_swp_mkuffd_wp(pte_t pte)
+{
+ return pte_wrprotect(__pte(pte_val(pte) | _PAGE_SWP_UFFD_WP));
+}
+
+static inline pte_t pte_swp_clear_uffd_wp(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD_WP));
+}
+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
+
/* static inline pte_t pte_mkread(pte_t pte) */
static inline pte_t pte_mkwrite_novma(pte_t pte)
@@ -783,6 +815,38 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
}
+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
+static inline int pmd_uffd_wp(pmd_t pmd)
+{
+ return pte_uffd_wp(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_mkuffd_wp(pmd_t pmd)
+{
+ return pte_pmd(pte_mkuffd_wp(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd)
+{
+ return pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd)));
+}
+
+static inline int pmd_swp_uffd_wp(pmd_t pmd)
+{
+ return pte_swp_uffd_wp(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd)
+{
+ return pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd)
+{
+ return pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd)));
+}
+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
+
#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
static inline int pmd_soft_dirty(pmd_t pmd)
{
@@ -907,7 +971,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
* Format of swap PTE:
* bit 0: _PAGE_PRESENT (zero)
* bit 1 to 3: _PAGE_LEAF (zero)
- * bit 4: _PAGE_SWP_SOFT_DIRTY
+ * bit 4: _PAGE_SWP_SOFT_DIRTY or _PAGE_SWP_UFFD_WP
* bit 5: _PAGE_PROT_NONE (zero)
* bit 6: exclusive marker
* bits 7 to 11: swap type
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support
2024-08-30 1:11 ` [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support Chunyan Zhang
@ 2024-08-30 1:31 ` Jinjie Ruan
2024-08-30 2:31 ` Chunyan Zhang
2024-11-05 13:13 ` Alexandre Ghiti
1 sibling, 1 reply; 15+ messages in thread
From: Jinjie Ruan @ 2024-08-30 1:31 UTC (permalink / raw)
To: Chunyan Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Andrew Morton, Alexandre Ghiti
Cc: linux-riscv, linux-kernel, Chunyan Zhang
On 2024/8/30 9:11, Chunyan Zhang wrote:
> The PTE bit(9) is reserved for software, now used by DEVMAP,
> this patch reuse bit(9) for soft-dirty which is enabled only
> if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
> and devmap will be mutually exclusive on RISC-V.
>
> To add swap PTE soft-dirty tracking, we borrow bit (4) which is
> available for swap PTEs on RISC-V systems.
>
> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> ---
> arch/riscv/Kconfig | 27 ++++++++++-
> arch/riscv/include/asm/pgtable-bits.h | 12 +++++
> arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
> 3 files changed, 106 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 0f3cd7c3a436..f1460fc01cd4 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -39,7 +39,6 @@ config RISCV
> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> select ARCH_HAS_PMEM_API
> select ARCH_HAS_PREPARE_SYNC_CORE_CMD
> - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
> select ARCH_HAS_PTE_SPECIAL
> select ARCH_HAS_SET_DIRECT_MAP if MMU
> select ARCH_HAS_SET_MEMORY if MMU
> @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
>
> If unsure, say N.
>
> +choice
> + prompt "PET RSW Bit(9) used for"
> + default RISCV_HAS_PTE_DEVMEP
> + depends on MMU && 64BIT
> + help
> + RISC-V PTE bit(9) is reserved for software, and used by more than
> + one kernel features which cannot be supported at the same time.
> + So we have to select one for it.
> +
> +config RISCV_HAS_PTE_DEVMEP
> + bool "DEVMAP mark"
> + select ARCH_HAS_PTE_DEVMAP
> + help
> + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
> + PTEs support to function.
> +
> + So if you want to use ZONE_DEVICE, select this.
> +
> +config RISCV_HAS_SOFT_DIRTY
> + bool "soft dirty"
> + select HAVE_ARCH_SOFT_DIRTY
> + help
> + The PTE bit(9) is used for soft-dirty tracking.
> +
> +endchoice
> +
Hi, ARCH_HAS_PTE_DEVMAP will be removed in following patch, I guess
riscv will too:
https://lore.kernel.org/all/47c26640cd85f3db2e0a2796047199bb984d1b3f.1719386613.git-series.apopple@nvidia.com/
> endmenu # "Kernel features"
>
> menu "Boot options"
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index 5bcc73430829..c6d51fe9fc6f 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -26,6 +26,18 @@
> #define _PAGE_DEVMAP 0
> #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
>
> +#ifdef CONFIG_MEM_SOFT_DIRTY
> +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
> +/*
> + * BIT 4 is not involved into swap entry computation, so we
> + * can borrow it for swap page soft-dirty tracking.
> + */
> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
> +#else
> +#define _PAGE_SOFT_DIRTY 0
> +#define _PAGE_SWP_SOFT_DIRTY 0
> +#endif /* CONFIG_MEM_SOFT_DIRTY */
> +
> #define _PAGE_TABLE _PAGE_PRESENT
>
> /*
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 089f3c9f56a3..d41507919ef2 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>
> static inline pte_t pte_mkdirty(pte_t pte)
> {
> - return __pte(pte_val(pte) | _PAGE_DIRTY);
> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> }
>
> static inline pte_t pte_mkclean(pte_t pte)
> @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> return pte;
> }
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline int pte_soft_dirty(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_SOFT_DIRTY;
> +}
> +
> +static inline pte_t pte_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> +}
> +
> +static inline int pte_swp_soft_dirty(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
> +}
> +
> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> +}
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> #ifdef CONFIG_RISCV_ISA_SVNAPOT
> #define pte_leaf_size(pte) (pte_napot(pte) ? \
> napot_cont_size(napot_cont_order(pte)) :\
> @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> }
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline int pmd_soft_dirty(pmd_t pmd)
> +{
> + return pte_soft_dirty(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> +}
> +
> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> +static inline int pmd_swp_soft_dirty(pmd_t pmd)
> +{
> + return pte_swp_soft_dirty(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> +}
> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> pmd_t *pmdp, pmd_t pmd)
> {
> @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> * Format of swap PTE:
> * bit 0: _PAGE_PRESENT (zero)
> * bit 1 to 3: _PAGE_LEAF (zero)
> + * bit 4: _PAGE_SWP_SOFT_DIRTY
> * bit 5: _PAGE_PROT_NONE (zero)
> * bit 6: exclusive marker
> * bits 7 to 11: swap type
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 3/3] riscv: mm: Add uffd write-protect support
2024-08-30 1:11 ` [RESEND PATCH V4 3/3] riscv: mm: Add uffd write-protect support Chunyan Zhang
@ 2024-08-30 1:34 ` Jinjie Ruan
2024-11-05 13:24 ` Alexandre Ghiti
1 sibling, 0 replies; 15+ messages in thread
From: Jinjie Ruan @ 2024-08-30 1:34 UTC (permalink / raw)
To: Chunyan Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Andrew Morton, Alexandre Ghiti
Cc: linux-riscv, linux-kernel, Chunyan Zhang
On 2024/8/30 9:11, Chunyan Zhang wrote:
> Reuse PTE bit(9) to do uffd-wp tracking and make it mutually exclusive
> with soft-dirty and DEVMAP which all use this PTE bit.
>
> Additionally for tracking the uffd-wp state as a PTE swap bit,
> we use swap entry pte bit(4) which is also used by swap
> soft-dirty tracking.
>
> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
Hi, I have submitted a similar patch below before rebased on commit
216e04bf1e4d ("riscv: mm: Add support for ZONE_DEVICE")
has been removed:
https://lore.kernel.org/all/20240730095325.3540198-1-ruanjinjie@huawei.com/
> ---
> arch/riscv/Kconfig | 7 +++
> arch/riscv/include/asm/pgtable-bits.h | 13 ++++++
> arch/riscv/include/asm/pgtable.h | 66 ++++++++++++++++++++++++++-
> 3 files changed, 85 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index f1460fc01cd4..aa595a5ed4b8 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -971,6 +971,13 @@ config RISCV_HAS_SOFT_DIRTY
> help
> The PTE bit(9) is used for soft-dirty tracking.
>
> +config RISCV_HAS_USERFAULTFD_WP
> + bool "userfaultfd write protection"
> + select HAVE_ARCH_USERFAULTFD_WP
> + depends on USERFAULTFD
> + help
> + The PTE bit(9) is used for userfaultfd write-protected
> + tracking.
> endchoice
>
> endmenu # "Kernel features"
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index c6d51fe9fc6f..7de16141c049 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -38,6 +38,19 @@
> #define _PAGE_SWP_SOFT_DIRTY 0
> #endif /* CONFIG_MEM_SOFT_DIRTY */
>
> +#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
> +/*
> + * CONFIG_HAVE_ARCH_USERFAULTFD_WP is mutually exclusive with
> + * HAVE_ARCH_SOFT_DIRTY so we can use the same bit for uffd-wp
> + * and soft-dirty tracking.
> + */
> +#define _PAGE_UFFD_WP (1 << 9) /* RSW: 0x2 for uffd-wp tracking */
> +#define _PAGE_SWP_UFFD_WP _PAGE_USER
> +#else
> +#define _PAGE_UFFD_WP 0
> +#define _PAGE_SWP_UFFD_WP 0
> +#endif
> +
> #define _PAGE_TABLE _PAGE_PRESENT
>
> /*
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index d41507919ef2..6ce4c9ba862a 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -417,6 +417,38 @@ static inline pte_t pte_wrprotect(pte_t pte)
> return __pte(pte_val(pte) & ~(_PAGE_WRITE));
> }
>
> +#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
> +static inline int pte_uffd_wp(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_UFFD_WP;
> +}
> +
> +static inline pte_t pte_mkuffd_wp(pte_t pte)
> +{
> + return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD_WP));
> +}
> +
> +static inline pte_t pte_clear_uffd_wp(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_UFFD_WP));
> +}
> +
> +static inline int pte_swp_uffd_wp(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_SWP_UFFD_WP;
> +}
> +
> +static inline pte_t pte_swp_mkuffd_wp(pte_t pte)
> +{
> + return pte_wrprotect(__pte(pte_val(pte) | _PAGE_SWP_UFFD_WP));
> +}
> +
> +static inline pte_t pte_swp_clear_uffd_wp(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD_WP));
> +}
> +#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
> +
> /* static inline pte_t pte_mkread(pte_t pte) */
>
> static inline pte_t pte_mkwrite_novma(pte_t pte)
> @@ -783,6 +815,38 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> }
>
> +#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
> +static inline int pmd_uffd_wp(pmd_t pmd)
> +{
> + return pte_uffd_wp(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_mkuffd_wp(pmd_t pmd)
> +{
> + return pte_pmd(pte_mkuffd_wp(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd)
> +{
> + return pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd)));
> +}
> +
> +static inline int pmd_swp_uffd_wp(pmd_t pmd)
> +{
> + return pte_swp_uffd_wp(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd)));
> +}
> +#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
> +
> #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> static inline int pmd_soft_dirty(pmd_t pmd)
> {
> @@ -907,7 +971,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> * Format of swap PTE:
> * bit 0: _PAGE_PRESENT (zero)
> * bit 1 to 3: _PAGE_LEAF (zero)
> - * bit 4: _PAGE_SWP_SOFT_DIRTY
> + * bit 4: _PAGE_SWP_SOFT_DIRTY or _PAGE_SWP_UFFD_WP
> * bit 5: _PAGE_PROT_NONE (zero)
> * bit 6: exclusive marker
> * bits 7 to 11: swap type
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support
2024-08-30 1:31 ` Jinjie Ruan
@ 2024-08-30 2:31 ` Chunyan Zhang
2024-11-05 13:14 ` Alexandre Ghiti
0 siblings, 1 reply; 15+ messages in thread
From: Chunyan Zhang @ 2024-08-30 2:31 UTC (permalink / raw)
To: Jinjie Ruan
Cc: Chunyan Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Andrew Morton, Alexandre Ghiti, linux-riscv, linux-kernel,
Björn Töpel
Hi Jinjie,
On Fri, 30 Aug 2024 at 09:31, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
>
>
>
> On 2024/8/30 9:11, Chunyan Zhang wrote:
> > The PTE bit(9) is reserved for software, now used by DEVMAP,
> > this patch reuse bit(9) for soft-dirty which is enabled only
> > if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
> > and devmap will be mutually exclusive on RISC-V.
> >
> > To add swap PTE soft-dirty tracking, we borrow bit (4) which is
> > available for swap PTEs on RISC-V systems.
> >
> > Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> > ---
> > arch/riscv/Kconfig | 27 ++++++++++-
> > arch/riscv/include/asm/pgtable-bits.h | 12 +++++
> > arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
> > 3 files changed, 106 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 0f3cd7c3a436..f1460fc01cd4 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -39,7 +39,6 @@ config RISCV
> > select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> > select ARCH_HAS_PMEM_API
> > select ARCH_HAS_PREPARE_SYNC_CORE_CMD
> > - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
> > select ARCH_HAS_PTE_SPECIAL
> > select ARCH_HAS_SET_DIRECT_MAP if MMU
> > select ARCH_HAS_SET_MEMORY if MMU
> > @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
> >
> > If unsure, say N.
> >
> > +choice
> > + prompt "PET RSW Bit(9) used for"
> > + default RISCV_HAS_PTE_DEVMEP
> > + depends on MMU && 64BIT
> > + help
> > + RISC-V PTE bit(9) is reserved for software, and used by more than
> > + one kernel features which cannot be supported at the same time.
> > + So we have to select one for it.
> > +
> > +config RISCV_HAS_PTE_DEVMEP
> > + bool "DEVMAP mark"
> > + select ARCH_HAS_PTE_DEVMAP
> > + help
> > + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
> > + PTEs support to function.
> > +
> > + So if you want to use ZONE_DEVICE, select this.
> > +
> > +config RISCV_HAS_SOFT_DIRTY
> > + bool "soft dirty"
> > + select HAVE_ARCH_SOFT_DIRTY
> > + help
> > + The PTE bit(9) is used for soft-dirty tracking.
> > +
> > +endchoice
> > +
>
> Hi, ARCH_HAS_PTE_DEVMAP will be removed in following patch, I guess
> riscv will too:
>
> https://lore.kernel.org/all/47c26640cd85f3db2e0a2796047199bb984d1b3f.1719386613.git-series.apopple@nvidia.com/
Thanks for sharing, I didn't notice this.
It looks like we should remove PTE_DEVMAP first and then add soft
dirty and uffd_wp.
Thanks,
Chunyan
>
> > endmenu # "Kernel features"
> >
> > menu "Boot options"
> > diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> > index 5bcc73430829..c6d51fe9fc6f 100644
> > --- a/arch/riscv/include/asm/pgtable-bits.h
> > +++ b/arch/riscv/include/asm/pgtable-bits.h
> > @@ -26,6 +26,18 @@
> > #define _PAGE_DEVMAP 0
> > #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
> >
> > +#ifdef CONFIG_MEM_SOFT_DIRTY
> > +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
> > +/*
> > + * BIT 4 is not involved into swap entry computation, so we
> > + * can borrow it for swap page soft-dirty tracking.
> > + */
> > +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
> > +#else
> > +#define _PAGE_SOFT_DIRTY 0
> > +#define _PAGE_SWP_SOFT_DIRTY 0
> > +#endif /* CONFIG_MEM_SOFT_DIRTY */
> > +
> > #define _PAGE_TABLE _PAGE_PRESENT
> >
> > /*
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 089f3c9f56a3..d41507919ef2 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
> >
> > static inline pte_t pte_mkdirty(pte_t pte)
> > {
> > - return __pte(pte_val(pte) | _PAGE_DIRTY);
> > + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> > }
> >
> > static inline pte_t pte_mkclean(pte_t pte)
> > @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> > return pte;
> > }
> >
> > +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> > +static inline int pte_soft_dirty(pte_t pte)
> > +{
> > + return pte_val(pte) & _PAGE_SOFT_DIRTY;
> > +}
> > +
> > +static inline pte_t pte_mksoft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> > +}
> > +
> > +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> > +}
> > +
> > +static inline int pte_swp_soft_dirty(pte_t pte)
> > +{
> > + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
> > +}
> > +
> > +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> > +}
> > +
> > +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> > +}
> > +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> > +
> > #ifdef CONFIG_RISCV_ISA_SVNAPOT
> > #define pte_leaf_size(pte) (pte_napot(pte) ? \
> > napot_cont_size(napot_cont_order(pte)) :\
> > @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> > return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> > }
> >
> > +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> > +static inline int pmd_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_soft_dirty(pmd_pte(pmd));
> > +}
> > +
> > +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> > +static inline int pmd_swp_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_swp_soft_dirty(pmd_pte(pmd));
> > +}
> > +
> > +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> > +}
> > +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> > +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> > +
> > static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> > pmd_t *pmdp, pmd_t pmd)
> > {
> > @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> > * Format of swap PTE:
> > * bit 0: _PAGE_PRESENT (zero)
> > * bit 1 to 3: _PAGE_LEAF (zero)
> > + * bit 4: _PAGE_SWP_SOFT_DIRTY
> > * bit 5: _PAGE_PROT_NONE (zero)
> > * bit 6: exclusive marker
> > * bits 7 to 11: swap type
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9)
2024-08-30 1:10 ` [RESEND PATCH V4 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9) Chunyan Zhang
@ 2024-11-05 12:45 ` Alexandre Ghiti
2024-11-06 6:32 ` Chunyan Zhang
0 siblings, 1 reply; 15+ messages in thread
From: Alexandre Ghiti @ 2024-11-05 12:45 UTC (permalink / raw)
To: Chunyan Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou, Andrew Morton
Cc: linux-riscv, linux-kernel, Chunyan Zhang
Hi Chunyan,
On 30/08/2024 03:10, Chunyan Zhang wrote:
> The PTE bit(9) on RISC-V is reserved for software, it is used by DEVMAP
> now which has to be disabled if we want to use bit(9) for other features,
> since there's no more free PTE bit on RISC-V now.
>
> So to make ARCH_HAS_PTE_DEVMAP selectable, this patch uses it as
> the build condition of devmap definitions.
>
> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> ---
> arch/riscv/include/asm/pgtable-64.h | 2 +-
> arch/riscv/include/asm/pgtable-bits.h | 6 ++++++
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> index 0897dd99ab8d..babb8d2b0f0b 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -398,7 +398,7 @@ static inline struct page *pgd_page(pgd_t pgd)
> #define p4d_offset p4d_offset
> p4d_t *p4d_offset(pgd_t *pgd, unsigned long address);
>
> -#ifdef CONFIG_TRANSPARENT_HUGEPAGE
> +#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && defined(CONFIG_ARCH_HAS_PTE_DEVMAP)
> static inline int pte_devmap(pte_t pte);
> static inline pte_t pmd_pte(pmd_t pmd);
>
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index a8f5205cea54..5bcc73430829 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -19,7 +19,13 @@
> #define _PAGE_SOFT (3 << 8) /* Reserved for software */
>
> #define _PAGE_SPECIAL (1 << 8) /* RSW: 0x1 */
> +
> +#ifdef CONFIG_ARCH_HAS_PTE_DEVMAP
> #define _PAGE_DEVMAP (1 << 9) /* RSW, devmap */
> +#else
> +#define _PAGE_DEVMAP 0
> +#endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
> +
> #define _PAGE_TABLE _PAGE_PRESENT
>
> /*
There is a small inconsistency in our code: pte_devmap() is protected by
a #ifdef but pte_mkdevmap() is not, I guess that's why you had to define
_PAGE_DEVMAP if !CONFIG_ARCH_HAS_PTE_DEVMAP.
I'd be in favor of removing the #ifdef around pte_devmap() too.
Thanks,
Alex
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support
2024-08-30 1:11 ` [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support Chunyan Zhang
2024-08-30 1:31 ` Jinjie Ruan
@ 2024-11-05 13:13 ` Alexandre Ghiti
2024-11-06 6:41 ` Chunyan Zhang
1 sibling, 1 reply; 15+ messages in thread
From: Alexandre Ghiti @ 2024-11-05 13:13 UTC (permalink / raw)
To: Chunyan Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou, Andrew Morton
Cc: linux-riscv, linux-kernel, Chunyan Zhang
On 30/08/2024 03:11, Chunyan Zhang wrote:
> The PTE bit(9) is reserved for software, now used by DEVMAP,
> this patch reuse bit(9) for soft-dirty which is enabled only
s/reuse/reuses
> if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
> and devmap will be mutually exclusive on RISC-V.
>
> To add swap PTE soft-dirty tracking, we borrow bit (4) which is
> available for swap PTEs on RISC-V systems.
>
> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> ---
> arch/riscv/Kconfig | 27 ++++++++++-
> arch/riscv/include/asm/pgtable-bits.h | 12 +++++
> arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
> 3 files changed, 106 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 0f3cd7c3a436..f1460fc01cd4 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -39,7 +39,6 @@ config RISCV
> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> select ARCH_HAS_PMEM_API
> select ARCH_HAS_PREPARE_SYNC_CORE_CMD
> - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
> select ARCH_HAS_PTE_SPECIAL
> select ARCH_HAS_SET_DIRECT_MAP if MMU
> select ARCH_HAS_SET_MEMORY if MMU
> @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
>
> If unsure, say N.
>
> +choice
> + prompt "PET RSW Bit(9) used for"
I would say: "PTE RSW bit(9) usage"
> + default RISCV_HAS_PTE_DEVMEP
s/DEVMEP/DEVMAP
> + depends on MMU && 64BIT
> + help
> + RISC-V PTE bit(9) is reserved for software, and used by more than
> + one kernel features which cannot be supported at the same time.
s/features/feature
> + So we have to select one for it.
> +
> +config RISCV_HAS_PTE_DEVMEP
> + bool "DEVMAP mark"
I would say simply "devmap"
> + select ARCH_HAS_PTE_DEVMAP
> + help
> + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
"is used for devmap...pages need devmap"
> + PTEs support to function.
> +
> + So if you want to use ZONE_DEVICE, select this.
> +
> +config RISCV_HAS_SOFT_DIRTY
> + bool "soft dirty"
s/soft dirty/soft-dirty
> + select HAVE_ARCH_SOFT_DIRTY
> + help
> + The PTE bit(9) is used for soft-dirty tracking.
> +
> +endchoice
> +
> endmenu # "Kernel features"
>
> menu "Boot options"
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index 5bcc73430829..c6d51fe9fc6f 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -26,6 +26,18 @@
> #define _PAGE_DEVMAP 0
> #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
>
> +#ifdef CONFIG_MEM_SOFT_DIRTY
For consistency with CONFIG_ARCH_HAS_PTE_DEVMAP, I would use
CONFIG_HAVE_ARCH_SOFT_DIRTY
> +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
> +/*
> + * BIT 4 is not involved into swap entry computation, so we
> + * can borrow it for swap page soft-dirty tracking.
> + */
> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
> +#else
> +#define _PAGE_SOFT_DIRTY 0
> +#define _PAGE_SWP_SOFT_DIRTY 0
> +#endif /* CONFIG_MEM_SOFT_DIRTY */
Same here.
> +
> #define _PAGE_TABLE _PAGE_PRESENT
>
> /*
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 089f3c9f56a3..d41507919ef2 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>
> static inline pte_t pte_mkdirty(pte_t pte)
> {
> - return __pte(pte_val(pte) | _PAGE_DIRTY);
> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> }
>
> static inline pte_t pte_mkclean(pte_t pte)
> @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> return pte;
> }
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline int pte_soft_dirty(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_SOFT_DIRTY;
> +}
> +
> +static inline pte_t pte_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> +}
> +
> +static inline int pte_swp_soft_dirty(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
> +}
> +
> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> +}
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> #ifdef CONFIG_RISCV_ISA_SVNAPOT
> #define pte_leaf_size(pte) (pte_napot(pte) ? \
> napot_cont_size(napot_cont_order(pte)) :\
> @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> }
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline int pmd_soft_dirty(pmd_t pmd)
> +{
> + return pte_soft_dirty(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> +}
> +
> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> +static inline int pmd_swp_soft_dirty(pmd_t pmd)
> +{
> + return pte_swp_soft_dirty(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> +}
> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> pmd_t *pmdp, pmd_t pmd)
> {
> @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> * Format of swap PTE:
> * bit 0: _PAGE_PRESENT (zero)
> * bit 1 to 3: _PAGE_LEAF (zero)
> + * bit 4: _PAGE_SWP_SOFT_DIRTY
> * bit 5: _PAGE_PROT_NONE (zero)
> * bit 6: exclusive marker
> * bits 7 to 11: swap type
Apart from the minor things above, the rest looks good so you can add:
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks,
Alex
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support
2024-08-30 2:31 ` Chunyan Zhang
@ 2024-11-05 13:14 ` Alexandre Ghiti
2024-11-06 2:34 ` Jinjie Ruan
2024-11-06 6:42 ` Chunyan Zhang
0 siblings, 2 replies; 15+ messages in thread
From: Alexandre Ghiti @ 2024-11-05 13:14 UTC (permalink / raw)
To: Chunyan Zhang, Jinjie Ruan
Cc: Chunyan Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Andrew Morton, linux-riscv, linux-kernel, Björn Töpel
On 30/08/2024 04:31, Chunyan Zhang wrote:
> Hi Jinjie,
>
> On Fri, 30 Aug 2024 at 09:31, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
>>
>>
>> On 2024/8/30 9:11, Chunyan Zhang wrote:
>>> The PTE bit(9) is reserved for software, now used by DEVMAP,
>>> this patch reuse bit(9) for soft-dirty which is enabled only
>>> if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
>>> and devmap will be mutually exclusive on RISC-V.
>>>
>>> To add swap PTE soft-dirty tracking, we borrow bit (4) which is
>>> available for swap PTEs on RISC-V systems.
>>>
>>> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
>>> ---
>>> arch/riscv/Kconfig | 27 ++++++++++-
>>> arch/riscv/include/asm/pgtable-bits.h | 12 +++++
>>> arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
>>> 3 files changed, 106 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>>> index 0f3cd7c3a436..f1460fc01cd4 100644
>>> --- a/arch/riscv/Kconfig
>>> +++ b/arch/riscv/Kconfig
>>> @@ -39,7 +39,6 @@ config RISCV
>>> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
>>> select ARCH_HAS_PMEM_API
>>> select ARCH_HAS_PREPARE_SYNC_CORE_CMD
>>> - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
>>> select ARCH_HAS_PTE_SPECIAL
>>> select ARCH_HAS_SET_DIRECT_MAP if MMU
>>> select ARCH_HAS_SET_MEMORY if MMU
>>> @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
>>>
>>> If unsure, say N.
>>>
>>> +choice
>>> + prompt "PET RSW Bit(9) used for"
>>> + default RISCV_HAS_PTE_DEVMEP
>>> + depends on MMU && 64BIT
>>> + help
>>> + RISC-V PTE bit(9) is reserved for software, and used by more than
>>> + one kernel features which cannot be supported at the same time.
>>> + So we have to select one for it.
>>> +
>>> +config RISCV_HAS_PTE_DEVMEP
>>> + bool "DEVMAP mark"
>>> + select ARCH_HAS_PTE_DEVMAP
>>> + help
>>> + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
>>> + PTEs support to function.
>>> +
>>> + So if you want to use ZONE_DEVICE, select this.
>>> +
>>> +config RISCV_HAS_SOFT_DIRTY
>>> + bool "soft dirty"
>>> + select HAVE_ARCH_SOFT_DIRTY
>>> + help
>>> + The PTE bit(9) is used for soft-dirty tracking.
>>> +
>>> +endchoice
>>> +
>> Hi, ARCH_HAS_PTE_DEVMAP will be removed in following patch, I guess
>> riscv will too:
>>
>> https://lore.kernel.org/all/47c26640cd85f3db2e0a2796047199bb984d1b3f.1719386613.git-series.apopple@nvidia.com/
> Thanks for sharing, I didn't notice this.
> It looks like we should remove PTE_DEVMAP first and then add soft
> dirty and uffd_wp.
I have not seen any progress in the removal of PTE_DEVMAP so I'd say we
should keep going with your patchset and we can still remove devmap later.
Thanks,
Alex
>
> Thanks,
> Chunyan
>
>>> endmenu # "Kernel features"
>>>
>>> menu "Boot options"
>>> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
>>> index 5bcc73430829..c6d51fe9fc6f 100644
>>> --- a/arch/riscv/include/asm/pgtable-bits.h
>>> +++ b/arch/riscv/include/asm/pgtable-bits.h
>>> @@ -26,6 +26,18 @@
>>> #define _PAGE_DEVMAP 0
>>> #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
>>>
>>> +#ifdef CONFIG_MEM_SOFT_DIRTY
>>> +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
>>> +/*
>>> + * BIT 4 is not involved into swap entry computation, so we
>>> + * can borrow it for swap page soft-dirty tracking.
>>> + */
>>> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
>>> +#else
>>> +#define _PAGE_SOFT_DIRTY 0
>>> +#define _PAGE_SWP_SOFT_DIRTY 0
>>> +#endif /* CONFIG_MEM_SOFT_DIRTY */
>>> +
>>> #define _PAGE_TABLE _PAGE_PRESENT
>>>
>>> /*
>>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>>> index 089f3c9f56a3..d41507919ef2 100644
>>> --- a/arch/riscv/include/asm/pgtable.h
>>> +++ b/arch/riscv/include/asm/pgtable.h
>>> @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>>>
>>> static inline pte_t pte_mkdirty(pte_t pte)
>>> {
>>> - return __pte(pte_val(pte) | _PAGE_DIRTY);
>>> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
>>> }
>>>
>>> static inline pte_t pte_mkclean(pte_t pte)
>>> @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
>>> return pte;
>>> }
>>>
>>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>>> +static inline int pte_soft_dirty(pte_t pte)
>>> +{
>>> + return pte_val(pte) & _PAGE_SOFT_DIRTY;
>>> +}
>>> +
>>> +static inline pte_t pte_mksoft_dirty(pte_t pte)
>>> +{
>>> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
>>> +}
>>> +
>>> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
>>> +{
>>> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
>>> +}
>>> +
>>> +static inline int pte_swp_soft_dirty(pte_t pte)
>>> +{
>>> + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
>>> +}
>>> +
>>> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
>>> +{
>>> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
>>> +}
>>> +
>>> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
>>> +{
>>> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
>>> +}
>>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>>> +
>>> #ifdef CONFIG_RISCV_ISA_SVNAPOT
>>> #define pte_leaf_size(pte) (pte_napot(pte) ? \
>>> napot_cont_size(napot_cont_order(pte)) :\
>>> @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
>>> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
>>> }
>>>
>>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>>> +static inline int pmd_soft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_soft_dirty(pmd_pte(pmd));
>>> +}
>>> +
>>> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
>>> +}
>>> +
>>> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
>>> +}
>>> +
>>> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
>>> +static inline int pmd_swp_soft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_swp_soft_dirty(pmd_pte(pmd));
>>> +}
>>> +
>>> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
>>> +}
>>> +
>>> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
>>> +}
>>> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
>>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>>> +
>>> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
>>> pmd_t *pmdp, pmd_t pmd)
>>> {
>>> @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
>>> * Format of swap PTE:
>>> * bit 0: _PAGE_PRESENT (zero)
>>> * bit 1 to 3: _PAGE_LEAF (zero)
>>> + * bit 4: _PAGE_SWP_SOFT_DIRTY
>>> * bit 5: _PAGE_PROT_NONE (zero)
>>> * bit 6: exclusive marker
>>> * bits 7 to 11: swap type
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 3/3] riscv: mm: Add uffd write-protect support
2024-08-30 1:11 ` [RESEND PATCH V4 3/3] riscv: mm: Add uffd write-protect support Chunyan Zhang
2024-08-30 1:34 ` Jinjie Ruan
@ 2024-11-05 13:24 ` Alexandre Ghiti
1 sibling, 0 replies; 15+ messages in thread
From: Alexandre Ghiti @ 2024-11-05 13:24 UTC (permalink / raw)
To: Chunyan Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou, Andrew Morton
Cc: linux-riscv, linux-kernel, Chunyan Zhang
On 30/08/2024 03:11, Chunyan Zhang wrote:
> Reuse PTE bit(9) to do uffd-wp tracking and make it mutually exclusive
> with soft-dirty and DEVMAP which all use this PTE bit.
>
> Additionally for tracking the uffd-wp state as a PTE swap bit,
> we use swap entry pte bit(4) which is also used by swap
> soft-dirty tracking.
>
> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> ---
> arch/riscv/Kconfig | 7 +++
> arch/riscv/include/asm/pgtable-bits.h | 13 ++++++
> arch/riscv/include/asm/pgtable.h | 66 ++++++++++++++++++++++++++-
> 3 files changed, 85 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index f1460fc01cd4..aa595a5ed4b8 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -971,6 +971,13 @@ config RISCV_HAS_SOFT_DIRTY
> help
> The PTE bit(9) is used for soft-dirty tracking.
>
> +config RISCV_HAS_USERFAULTFD_WP
> + bool "userfaultfd write protection"
> + select HAVE_ARCH_USERFAULTFD_WP
> + depends on USERFAULTFD
> + help
> + The PTE bit(9) is used for userfaultfd write-protected
> + tracking.
> endchoice
>
> endmenu # "Kernel features"
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index c6d51fe9fc6f..7de16141c049 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -38,6 +38,19 @@
> #define _PAGE_SWP_SOFT_DIRTY 0
> #endif /* CONFIG_MEM_SOFT_DIRTY */
>
> +#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
> +/*
> + * CONFIG_HAVE_ARCH_USERFAULTFD_WP is mutually exclusive with
> + * HAVE_ARCH_SOFT_DIRTY so we can use the same bit for uffd-wp
> + * and soft-dirty tracking.
> + */
> +#define _PAGE_UFFD_WP (1 << 9) /* RSW: 0x2 for uffd-wp tracking */
> +#define _PAGE_SWP_UFFD_WP _PAGE_USER
> +#else
> +#define _PAGE_UFFD_WP 0
> +#define _PAGE_SWP_UFFD_WP 0
> +#endif
> +
> #define _PAGE_TABLE _PAGE_PRESENT
>
> /*
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index d41507919ef2..6ce4c9ba862a 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -417,6 +417,38 @@ static inline pte_t pte_wrprotect(pte_t pte)
> return __pte(pte_val(pte) & ~(_PAGE_WRITE));
> }
>
> +#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
> +static inline int pte_uffd_wp(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_UFFD_WP;
> +}
> +
> +static inline pte_t pte_mkuffd_wp(pte_t pte)
> +{
> + return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD_WP));
> +}
> +
> +static inline pte_t pte_clear_uffd_wp(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_UFFD_WP));
> +}
> +
> +static inline int pte_swp_uffd_wp(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_SWP_UFFD_WP;
> +}
> +
> +static inline pte_t pte_swp_mkuffd_wp(pte_t pte)
> +{
> + return pte_wrprotect(__pte(pte_val(pte) | _PAGE_SWP_UFFD_WP));
> +}
Weird to wrprotect a swap entry here, given x86/arm64 don't do that, you
should remove it.
> +
> +static inline pte_t pte_swp_clear_uffd_wp(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD_WP));
> +}
> +#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
> +
> /* static inline pte_t pte_mkread(pte_t pte) */
>
> static inline pte_t pte_mkwrite_novma(pte_t pte)
> @@ -783,6 +815,38 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> }
>
> +#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
> +static inline int pmd_uffd_wp(pmd_t pmd)
> +{
> + return pte_uffd_wp(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_mkuffd_wp(pmd_t pmd)
> +{
> + return pte_pmd(pte_mkuffd_wp(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd)
> +{
> + return pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd)));
> +}
> +
> +static inline int pmd_swp_uffd_wp(pmd_t pmd)
> +{
> + return pte_swp_uffd_wp(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd)));
> +}
> +#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
> +
> #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> static inline int pmd_soft_dirty(pmd_t pmd)
> {
> @@ -907,7 +971,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> * Format of swap PTE:
> * bit 0: _PAGE_PRESENT (zero)
> * bit 1 to 3: _PAGE_LEAF (zero)
> - * bit 4: _PAGE_SWP_SOFT_DIRTY
> + * bit 4: _PAGE_SWP_SOFT_DIRTY or _PAGE_SWP_UFFD_WP
> * bit 5: _PAGE_PROT_NONE (zero)
> * bit 6: exclusive marker
> * bits 7 to 11: swap type
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support
2024-11-05 13:14 ` Alexandre Ghiti
@ 2024-11-06 2:34 ` Jinjie Ruan
2024-11-06 6:42 ` Chunyan Zhang
1 sibling, 0 replies; 15+ messages in thread
From: Jinjie Ruan @ 2024-11-06 2:34 UTC (permalink / raw)
To: Alexandre Ghiti, Chunyan Zhang
Cc: Chunyan Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Andrew Morton, linux-riscv, linux-kernel, Björn Töpel
On 2024/11/5 21:14, Alexandre Ghiti wrote:
> On 30/08/2024 04:31, Chunyan Zhang wrote:
>> Hi Jinjie,
>>
>> On Fri, 30 Aug 2024 at 09:31, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
>>>
>>>
>>> On 2024/8/30 9:11, Chunyan Zhang wrote:
>>>> The PTE bit(9) is reserved for software, now used by DEVMAP,
>>>> this patch reuse bit(9) for soft-dirty which is enabled only
>>>> if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
>>>> and devmap will be mutually exclusive on RISC-V.
>>>>
>>>> To add swap PTE soft-dirty tracking, we borrow bit (4) which is
>>>> available for swap PTEs on RISC-V systems.
>>>>
>>>> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
>>>> ---
>>>> arch/riscv/Kconfig | 27 ++++++++++-
>>>> arch/riscv/include/asm/pgtable-bits.h | 12 +++++
>>>> arch/riscv/include/asm/pgtable.h | 69
>>>> ++++++++++++++++++++++++++-
>>>> 3 files changed, 106 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>>>> index 0f3cd7c3a436..f1460fc01cd4 100644
>>>> --- a/arch/riscv/Kconfig
>>>> +++ b/arch/riscv/Kconfig
>>>> @@ -39,7 +39,6 @@ config RISCV
>>>> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
>>>> select ARCH_HAS_PMEM_API
>>>> select ARCH_HAS_PREPARE_SYNC_CORE_CMD
>>>> - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
>>>> select ARCH_HAS_PTE_SPECIAL
>>>> select ARCH_HAS_SET_DIRECT_MAP if MMU
>>>> select ARCH_HAS_SET_MEMORY if MMU
>>>> @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
>>>>
>>>> If unsure, say N.
>>>>
>>>> +choice
>>>> + prompt "PET RSW Bit(9) used for"
>>>> + default RISCV_HAS_PTE_DEVMEP
>>>> + depends on MMU && 64BIT
>>>> + help
>>>> + RISC-V PTE bit(9) is reserved for software, and used by more
>>>> than
>>>> + one kernel features which cannot be supported at the same time.
>>>> + So we have to select one for it.
>>>> +
>>>> +config RISCV_HAS_PTE_DEVMEP
>>>> + bool "DEVMAP mark"
>>>> + select ARCH_HAS_PTE_DEVMAP
>>>> + help
>>>> + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages
>>>> need DEVMAP
>>>> + PTEs support to function.
>>>> +
>>>> + So if you want to use ZONE_DEVICE, select this.
>>>> +
>>>> +config RISCV_HAS_SOFT_DIRTY
>>>> + bool "soft dirty"
>>>> + select HAVE_ARCH_SOFT_DIRTY
>>>> + help
>>>> + The PTE bit(9) is used for soft-dirty tracking.
>>>> +
>>>> +endchoice
>>>> +
>>> Hi, ARCH_HAS_PTE_DEVMAP will be removed in following patch, I guess
>>> riscv will too:
>>>
>>> https://lore.kernel.org/all/47c26640cd85f3db2e0a2796047199bb984d1b3f.1719386613.git-series.apopple@nvidia.com/
>> Thanks for sharing, I didn't notice this.
>> It looks like we should remove PTE_DEVMAP first and then add soft
>> dirty and uffd_wp.
>
>
> I have not seen any progress in the removal of PTE_DEVMAP so I'd say we
> should keep going with your patchset and we can still remove devmap later.
Sure, it is time to keep going on.
I started by implementing a patch similar to multiplexing bit 9, but
considering the above remove PTE_DEVMAP patch, so just gave it up.
>
> Thanks,
>
> Alex
>
>
>>
>> Thanks,
>> Chunyan
>>
>>>> endmenu # "Kernel features"
>>>>
>>>> menu "Boot options"
>>>> diff --git a/arch/riscv/include/asm/pgtable-bits.h
>>>> b/arch/riscv/include/asm/pgtable-bits.h
>>>> index 5bcc73430829..c6d51fe9fc6f 100644
>>>> --- a/arch/riscv/include/asm/pgtable-bits.h
>>>> +++ b/arch/riscv/include/asm/pgtable-bits.h
>>>> @@ -26,6 +26,18 @@
>>>> #define _PAGE_DEVMAP 0
>>>> #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
>>>>
>>>> +#ifdef CONFIG_MEM_SOFT_DIRTY
>>>> +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software
>>>> dirty tracking */
>>>> +/*
>>>> + * BIT 4 is not involved into swap entry computation, so we
>>>> + * can borrow it for swap page soft-dirty tracking.
>>>> + */
>>>> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
>>>> +#else
>>>> +#define _PAGE_SOFT_DIRTY 0
>>>> +#define _PAGE_SWP_SOFT_DIRTY 0
>>>> +#endif /* CONFIG_MEM_SOFT_DIRTY */
>>>> +
>>>> #define _PAGE_TABLE _PAGE_PRESENT
>>>>
>>>> /*
>>>> diff --git a/arch/riscv/include/asm/pgtable.h
>>>> b/arch/riscv/include/asm/pgtable.h
>>>> index 089f3c9f56a3..d41507919ef2 100644
>>>> --- a/arch/riscv/include/asm/pgtable.h
>>>> +++ b/arch/riscv/include/asm/pgtable.h
>>>> @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>>>>
>>>> static inline pte_t pte_mkdirty(pte_t pte)
>>>> {
>>>> - return __pte(pte_val(pte) | _PAGE_DIRTY);
>>>> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
>>>> }
>>>>
>>>> static inline pte_t pte_mkclean(pte_t pte)
>>>> @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
>>>> return pte;
>>>> }
>>>>
>>>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>>>> +static inline int pte_soft_dirty(pte_t pte)
>>>> +{
>>>> + return pte_val(pte) & _PAGE_SOFT_DIRTY;
>>>> +}
>>>> +
>>>> +static inline pte_t pte_mksoft_dirty(pte_t pte)
>>>> +{
>>>> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
>>>> +}
>>>> +
>>>> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
>>>> +{
>>>> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
>>>> +}
>>>> +
>>>> +static inline int pte_swp_soft_dirty(pte_t pte)
>>>> +{
>>>> + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
>>>> +}
>>>> +
>>>> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
>>>> +{
>>>> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
>>>> +}
>>>> +
>>>> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
>>>> +{
>>>> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
>>>> +}
>>>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>>>> +
>>>> #ifdef CONFIG_RISCV_ISA_SVNAPOT
>>>> #define pte_leaf_size(pte) (pte_napot(pte)
>>>> ? \
>>>>
>>>> napot_cont_size(napot_cont_order(pte)) :\
>>>> @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
>>>> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
>>>> }
>>>>
>>>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>>>> +static inline int pmd_soft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_soft_dirty(pmd_pte(pmd));
>>>> +}
>>>> +
>>>> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
>>>> +}
>>>> +
>>>> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
>>>> +}
>>>> +
>>>> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
>>>> +static inline int pmd_swp_soft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_swp_soft_dirty(pmd_pte(pmd));
>>>> +}
>>>> +
>>>> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
>>>> +}
>>>> +
>>>> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
>>>> +}
>>>> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
>>>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>>>> +
>>>> static inline void set_pmd_at(struct mm_struct *mm, unsigned long
>>>> addr,
>>>> pmd_t *pmdp, pmd_t pmd)
>>>> {
>>>> @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct
>>>> vm_area_struct *vma,
>>>> * Format of swap PTE:
>>>> * bit 0: _PAGE_PRESENT (zero)
>>>> * bit 1 to 3: _PAGE_LEAF (zero)
>>>> + * bit 4: _PAGE_SWP_SOFT_DIRTY
>>>> * bit 5: _PAGE_PROT_NONE (zero)
>>>> * bit 6: exclusive marker
>>>> * bits 7 to 11: swap type
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9)
2024-11-05 12:45 ` Alexandre Ghiti
@ 2024-11-06 6:32 ` Chunyan Zhang
0 siblings, 0 replies; 15+ messages in thread
From: Chunyan Zhang @ 2024-11-06 6:32 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Chunyan Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Andrew Morton, linux-riscv, linux-kernel
Hi Alex,
On Tue, 5 Nov 2024 at 20:45, Alexandre Ghiti <alex@ghiti.fr> wrote:
>
> Hi Chunyan,
>
> On 30/08/2024 03:10, Chunyan Zhang wrote:
> > The PTE bit(9) on RISC-V is reserved for software, it is used by DEVMAP
> > now which has to be disabled if we want to use bit(9) for other features,
> > since there's no more free PTE bit on RISC-V now.
> >
> > So to make ARCH_HAS_PTE_DEVMAP selectable, this patch uses it as
> > the build condition of devmap definitions.
> >
> > Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> > ---
> > arch/riscv/include/asm/pgtable-64.h | 2 +-
> > arch/riscv/include/asm/pgtable-bits.h | 6 ++++++
> > 2 files changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> > index 0897dd99ab8d..babb8d2b0f0b 100644
> > --- a/arch/riscv/include/asm/pgtable-64.h
> > +++ b/arch/riscv/include/asm/pgtable-64.h
> > @@ -398,7 +398,7 @@ static inline struct page *pgd_page(pgd_t pgd)
> > #define p4d_offset p4d_offset
> > p4d_t *p4d_offset(pgd_t *pgd, unsigned long address);
> >
> > -#ifdef CONFIG_TRANSPARENT_HUGEPAGE
> > +#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && defined(CONFIG_ARCH_HAS_PTE_DEVMAP)
> > static inline int pte_devmap(pte_t pte);
> > static inline pte_t pmd_pte(pmd_t pmd);
> >
> > diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> > index a8f5205cea54..5bcc73430829 100644
> > --- a/arch/riscv/include/asm/pgtable-bits.h
> > +++ b/arch/riscv/include/asm/pgtable-bits.h
> > @@ -19,7 +19,13 @@
> > #define _PAGE_SOFT (3 << 8) /* Reserved for software */
> >
> > #define _PAGE_SPECIAL (1 << 8) /* RSW: 0x1 */
> > +
> > +#ifdef CONFIG_ARCH_HAS_PTE_DEVMAP
> > #define _PAGE_DEVMAP (1 << 9) /* RSW, devmap */
> > +#else
> > +#define _PAGE_DEVMAP 0
> > +#endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
> > +
> > #define _PAGE_TABLE _PAGE_PRESENT
> >
> > /*
>
>
> There is a small inconsistency in our code: pte_devmap() is protected by
> a #ifdef but pte_mkdevmap() is not, I guess that's why you had to define
pte_devmap() is defined in include/linux/mm.h as well, we have to use
#ifdef to avoid compile error since we will change the
CONFIG_ARCH_HAS_PTE_DEVMAP to be selectable on riscv.
> _PAGE_DEVMAP if !CONFIG_ARCH_HAS_PTE_DEVMAP.
>
> I'd be in favor of removing the #ifdef around pte_devmap() too.
So we cannot remove the #ifdef here, the compiler would report
redefinition errors if CONFIG_ARCH_HAS_PTE_DEVMAP is not selected.
Thanks for the review,
Chunyan
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support
2024-11-05 13:13 ` Alexandre Ghiti
@ 2024-11-06 6:41 ` Chunyan Zhang
0 siblings, 0 replies; 15+ messages in thread
From: Chunyan Zhang @ 2024-11-06 6:41 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Chunyan Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Andrew Morton, linux-riscv, linux-kernel
On Tue, 5 Nov 2024 at 21:13, Alexandre Ghiti <alex@ghiti.fr> wrote:
>
> On 30/08/2024 03:11, Chunyan Zhang wrote:
> > The PTE bit(9) is reserved for software, now used by DEVMAP,
> > this patch reuse bit(9) for soft-dirty which is enabled only
>
>
> s/reuse/reuses
>
>
> > if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
> > and devmap will be mutually exclusive on RISC-V.
> >
> > To add swap PTE soft-dirty tracking, we borrow bit (4) which is
> > available for swap PTEs on RISC-V systems.
> >
> > Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> > ---
> > arch/riscv/Kconfig | 27 ++++++++++-
> > arch/riscv/include/asm/pgtable-bits.h | 12 +++++
> > arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
> > 3 files changed, 106 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 0f3cd7c3a436..f1460fc01cd4 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -39,7 +39,6 @@ config RISCV
> > select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> > select ARCH_HAS_PMEM_API
> > select ARCH_HAS_PREPARE_SYNC_CORE_CMD
> > - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
> > select ARCH_HAS_PTE_SPECIAL
> > select ARCH_HAS_SET_DIRECT_MAP if MMU
> > select ARCH_HAS_SET_MEMORY if MMU
> > @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
> >
> > If unsure, say N.
> >
> > +choice
> > + prompt "PET RSW Bit(9) used for"
>
>
> I would say: "PTE RSW bit(9) usage"
>
>
> > + default RISCV_HAS_PTE_DEVMEP
>
>
> s/DEVMEP/DEVMAP
>
>
> > + depends on MMU && 64BIT
> > + help
> > + RISC-V PTE bit(9) is reserved for software, and used by more than
> > + one kernel features which cannot be supported at the same time.
>
>
> s/features/feature
>
>
> > + So we have to select one for it.
> > +
> > +config RISCV_HAS_PTE_DEVMEP
> > + bool "DEVMAP mark"
>
>
> I would say simply "devmap"
Ok, only "devmap" without the following "mark", right?
>
>
> > + select ARCH_HAS_PTE_DEVMAP
> > + help
> > + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
>
>
> "is used for devmap...pages need devmap"
>
>
> > + PTEs support to function.
> > +
> > + So if you want to use ZONE_DEVICE, select this.
> > +
> > +config RISCV_HAS_SOFT_DIRTY
> > + bool "soft dirty"
>
>
> s/soft dirty/soft-dirty
>
>
> > + select HAVE_ARCH_SOFT_DIRTY
> > + help
> > + The PTE bit(9) is used for soft-dirty tracking.
> > +
> > +endchoice
> > +
> > endmenu # "Kernel features"
> >
> > menu "Boot options"
> > diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> > index 5bcc73430829..c6d51fe9fc6f 100644
> > --- a/arch/riscv/include/asm/pgtable-bits.h
> > +++ b/arch/riscv/include/asm/pgtable-bits.h
> > @@ -26,6 +26,18 @@
> > #define _PAGE_DEVMAP 0
> > #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
> >
> > +#ifdef CONFIG_MEM_SOFT_DIRTY
>
>
> For consistency with CONFIG_ARCH_HAS_PTE_DEVMAP, I would use
> CONFIG_HAVE_ARCH_SOFT_DIRTY
CONFIG_MEM_SOFT_DIRTY is not equal to the CONFIG_HAVE_ARCH_SOFT_DIRTY,
the latter is one of its dependencies.
If CONFIG_HAVE_ARCH_SOFT_DIRTY is selected, but CONFIG_MEM_SOFT_DIRTY
is not, the bit(9) should not be set/cleared by pte soft_dirty APIs?
Also considering x86 is using CONFIG_MEM_SOFT_DIRTY here, should we
keep the same?
>
>
> > +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
> > +/*
> > + * BIT 4 is not involved into swap entry computation, so we
> > + * can borrow it for swap page soft-dirty tracking.
> > + */
> > +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
> > +#else
> > +#define _PAGE_SOFT_DIRTY 0
> > +#define _PAGE_SWP_SOFT_DIRTY 0
> > +#endif /* CONFIG_MEM_SOFT_DIRTY */
>
>
> Same here.
>
>
> > +
> > #define _PAGE_TABLE _PAGE_PRESENT
> >
> > /*
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 089f3c9f56a3..d41507919ef2 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
> >
> > static inline pte_t pte_mkdirty(pte_t pte)
> > {
> > - return __pte(pte_val(pte) | _PAGE_DIRTY);
> > + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> > }
> >
> > static inline pte_t pte_mkclean(pte_t pte)
> > @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> > return pte;
> > }
> >
> > +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> > +static inline int pte_soft_dirty(pte_t pte)
> > +{
> > + return pte_val(pte) & _PAGE_SOFT_DIRTY;
> > +}
> > +
> > +static inline pte_t pte_mksoft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> > +}
> > +
> > +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> > +}
> > +
> > +static inline int pte_swp_soft_dirty(pte_t pte)
> > +{
> > + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
> > +}
> > +
> > +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> > +}
> > +
> > +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> > +}
> > +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> > +
> > #ifdef CONFIG_RISCV_ISA_SVNAPOT
> > #define pte_leaf_size(pte) (pte_napot(pte) ? \
> > napot_cont_size(napot_cont_order(pte)) :\
> > @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> > return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> > }
> >
> > +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> > +static inline int pmd_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_soft_dirty(pmd_pte(pmd));
> > +}
> > +
> > +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> > +static inline int pmd_swp_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_swp_soft_dirty(pmd_pte(pmd));
> > +}
> > +
> > +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> > +}
> > +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> > +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> > +
> > static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> > pmd_t *pmdp, pmd_t pmd)
> > {
> > @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> > * Format of swap PTE:
> > * bit 0: _PAGE_PRESENT (zero)
> > * bit 1 to 3: _PAGE_LEAF (zero)
> > + * bit 4: _PAGE_SWP_SOFT_DIRTY
> > * bit 5: _PAGE_PROT_NONE (zero)
> > * bit 6: exclusive marker
> > * bits 7 to 11: swap type
>
>
> Apart from the minor things above, the rest looks good so you can add:
>
> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks for the review,
Chunyan
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support
2024-11-05 13:14 ` Alexandre Ghiti
2024-11-06 2:34 ` Jinjie Ruan
@ 2024-11-06 6:42 ` Chunyan Zhang
1 sibling, 0 replies; 15+ messages in thread
From: Chunyan Zhang @ 2024-11-06 6:42 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Jinjie Ruan, Chunyan Zhang, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Andrew Morton, linux-riscv, linux-kernel,
Björn Töpel
Hi Alex,
On Tue, 5 Nov 2024 at 21:14, Alexandre Ghiti <alex@ghiti.fr> wrote:
>
> On 30/08/2024 04:31, Chunyan Zhang wrote:
> > Hi Jinjie,
> >
> > On Fri, 30 Aug 2024 at 09:31, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
> >>
> >>
> >> On 2024/8/30 9:11, Chunyan Zhang wrote:
> >>> The PTE bit(9) is reserved for software, now used by DEVMAP,
> >>> this patch reuse bit(9) for soft-dirty which is enabled only
> >>> if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
> >>> and devmap will be mutually exclusive on RISC-V.
> >>>
> >>> To add swap PTE soft-dirty tracking, we borrow bit (4) which is
> >>> available for swap PTEs on RISC-V systems.
> >>>
> >>> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> >>> ---
> >>> arch/riscv/Kconfig | 27 ++++++++++-
> >>> arch/riscv/include/asm/pgtable-bits.h | 12 +++++
> >>> arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
> >>> 3 files changed, 106 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >>> index 0f3cd7c3a436..f1460fc01cd4 100644
> >>> --- a/arch/riscv/Kconfig
> >>> +++ b/arch/riscv/Kconfig
> >>> @@ -39,7 +39,6 @@ config RISCV
> >>> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> >>> select ARCH_HAS_PMEM_API
> >>> select ARCH_HAS_PREPARE_SYNC_CORE_CMD
> >>> - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
> >>> select ARCH_HAS_PTE_SPECIAL
> >>> select ARCH_HAS_SET_DIRECT_MAP if MMU
> >>> select ARCH_HAS_SET_MEMORY if MMU
> >>> @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
> >>>
> >>> If unsure, say N.
> >>>
> >>> +choice
> >>> + prompt "PET RSW Bit(9) used for"
> >>> + default RISCV_HAS_PTE_DEVMEP
> >>> + depends on MMU && 64BIT
> >>> + help
> >>> + RISC-V PTE bit(9) is reserved for software, and used by more than
> >>> + one kernel features which cannot be supported at the same time.
> >>> + So we have to select one for it.
> >>> +
> >>> +config RISCV_HAS_PTE_DEVMEP
> >>> + bool "DEVMAP mark"
> >>> + select ARCH_HAS_PTE_DEVMAP
> >>> + help
> >>> + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
> >>> + PTEs support to function.
> >>> +
> >>> + So if you want to use ZONE_DEVICE, select this.
> >>> +
> >>> +config RISCV_HAS_SOFT_DIRTY
> >>> + bool "soft dirty"
> >>> + select HAVE_ARCH_SOFT_DIRTY
> >>> + help
> >>> + The PTE bit(9) is used for soft-dirty tracking.
> >>> +
> >>> +endchoice
> >>> +
> >> Hi, ARCH_HAS_PTE_DEVMAP will be removed in following patch, I guess
> >> riscv will too:
> >>
> >> https://lore.kernel.org/all/47c26640cd85f3db2e0a2796047199bb984d1b3f.1719386613.git-series.apopple@nvidia.com/
> > Thanks for sharing, I didn't notice this.
> > It looks like we should remove PTE_DEVMAP first and then add soft
> > dirty and uffd_wp.
>
>
> I have not seen any progress in the removal of PTE_DEVMAP so I'd say we
> should keep going with your patchset and we can still remove devmap later.
Okay, then I will update the patchset with addressing your comments.
Thanks for the review,
Chunyan
>
> Thanks,
>
> Alex
>
>
> >
> > Thanks,
> > Chunyan
> >
> >>> endmenu # "Kernel features"
> >>>
> >>> menu "Boot options"
> >>> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> >>> index 5bcc73430829..c6d51fe9fc6f 100644
> >>> --- a/arch/riscv/include/asm/pgtable-bits.h
> >>> +++ b/arch/riscv/include/asm/pgtable-bits.h
> >>> @@ -26,6 +26,18 @@
> >>> #define _PAGE_DEVMAP 0
> >>> #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
> >>>
> >>> +#ifdef CONFIG_MEM_SOFT_DIRTY
> >>> +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
> >>> +/*
> >>> + * BIT 4 is not involved into swap entry computation, so we
> >>> + * can borrow it for swap page soft-dirty tracking.
> >>> + */
> >>> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
> >>> +#else
> >>> +#define _PAGE_SOFT_DIRTY 0
> >>> +#define _PAGE_SWP_SOFT_DIRTY 0
> >>> +#endif /* CONFIG_MEM_SOFT_DIRTY */
> >>> +
> >>> #define _PAGE_TABLE _PAGE_PRESENT
> >>>
> >>> /*
> >>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> >>> index 089f3c9f56a3..d41507919ef2 100644
> >>> --- a/arch/riscv/include/asm/pgtable.h
> >>> +++ b/arch/riscv/include/asm/pgtable.h
> >>> @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
> >>>
> >>> static inline pte_t pte_mkdirty(pte_t pte)
> >>> {
> >>> - return __pte(pte_val(pte) | _PAGE_DIRTY);
> >>> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> >>> }
> >>>
> >>> static inline pte_t pte_mkclean(pte_t pte)
> >>> @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> >>> return pte;
> >>> }
> >>>
> >>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> >>> +static inline int pte_soft_dirty(pte_t pte)
> >>> +{
> >>> + return pte_val(pte) & _PAGE_SOFT_DIRTY;
> >>> +}
> >>> +
> >>> +static inline pte_t pte_mksoft_dirty(pte_t pte)
> >>> +{
> >>> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> >>> +}
> >>> +
> >>> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> >>> +{
> >>> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> >>> +}
> >>> +
> >>> +static inline int pte_swp_soft_dirty(pte_t pte)
> >>> +{
> >>> + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
> >>> +}
> >>> +
> >>> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> >>> +{
> >>> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> >>> +}
> >>> +
> >>> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> >>> +{
> >>> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> >>> +}
> >>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> >>> +
> >>> #ifdef CONFIG_RISCV_ISA_SVNAPOT
> >>> #define pte_leaf_size(pte) (pte_napot(pte) ? \
> >>> napot_cont_size(napot_cont_order(pte)) :\
> >>> @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> >>> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> >>> }
> >>>
> >>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> >>> +static inline int pmd_soft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_soft_dirty(pmd_pte(pmd));
> >>> +}
> >>> +
> >>> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> >>> +}
> >>> +
> >>> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> >>> +}
> >>> +
> >>> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> >>> +static inline int pmd_swp_soft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_swp_soft_dirty(pmd_pte(pmd));
> >>> +}
> >>> +
> >>> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> >>> +}
> >>> +
> >>> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> >>> +}
> >>> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> >>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> >>> +
> >>> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> >>> pmd_t *pmdp, pmd_t pmd)
> >>> {
> >>> @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> >>> * Format of swap PTE:
> >>> * bit 0: _PAGE_PRESENT (zero)
> >>> * bit 1 to 3: _PAGE_LEAF (zero)
> >>> + * bit 4: _PAGE_SWP_SOFT_DIRTY
> >>> * bit 5: _PAGE_PROT_NONE (zero)
> >>> * bit 6: exclusive marker
> >>> * bits 7 to 11: swap type
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2024-11-06 6:42 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-08-30 1:10 [RESEND PATCH V4 0/3] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
2024-08-30 1:10 ` [RESEND PATCH V4 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9) Chunyan Zhang
2024-11-05 12:45 ` Alexandre Ghiti
2024-11-06 6:32 ` Chunyan Zhang
2024-08-30 1:11 ` [RESEND PATCH V4 2/3] riscv: mm: Add soft-dirty page tracking support Chunyan Zhang
2024-08-30 1:31 ` Jinjie Ruan
2024-08-30 2:31 ` Chunyan Zhang
2024-11-05 13:14 ` Alexandre Ghiti
2024-11-06 2:34 ` Jinjie Ruan
2024-11-06 6:42 ` Chunyan Zhang
2024-11-05 13:13 ` Alexandre Ghiti
2024-11-06 6:41 ` Chunyan Zhang
2024-08-30 1:11 ` [RESEND PATCH V4 3/3] riscv: mm: Add uffd write-protect support Chunyan Zhang
2024-08-30 1:34 ` Jinjie Ruan
2024-11-05 13:24 ` Alexandre Ghiti
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