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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"Joao.Pinto@synopsys.com" <Joao.Pinto@synopsys.com>,
	"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH 1/8] bindings: PCI: designware: Example update
Date: Tue, 3 Apr 2018 16:22:01 +0530	[thread overview]
Message-ID: <c5ffa7d6-40b1-1702-c0fd-9ebb1b4197f8@ti.com> (raw)
In-Reply-To: <36a36857-2d79-2c2d-198d-a3b65cafc768@synopsys.com>



On Tuesday 03 April 2018 04:03 PM, Gustavo Pimentel wrote:
> Hi Kishon,
> 
> On 02/04/2018 06:23, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Wednesday 28 March 2018 05:08 PM, Gustavo Pimentel wrote:
>>> Changes the IP registers size to accommodate the ATU unroll space.
>>>
>>> Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers.
>>>
>>> Replaces the pcie base address example by a real pcie base address in use.
>>>
>>> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
>>> ---
>>>  Documentation/devicetree/bindings/pci/designware-pcie.txt | 12 ++++++------
>>>  1 file changed, 6 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>>> index 1da7ade..6300762 100644
>>> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
>>> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>>> @@ -1,7 +1,8 @@
>>>  * Synopsys DesignWare PCIe interface
>>>  
>>>  Required properties:
>>> -- compatible: should contain "snps,dw-pcie" to identify the core.
>>> +- compatible:
>>> +	"snps,dw-pcie" for RC mode;
>>
>> I think irrespective of RC mode or EP mode, "snps,dw-pcie" can be used to
>> identify the pcie core?
> 
> I guess so. What you suggest? I was just folling the same guideline present
> here: https://lkml.org/lkml/2017/11/3/310

Okay, I think you should have
"snps,dw-pcie-rc", "snps,dw-pcie" for RC mode;

and in the later patch
"snps,dw-pcie-ep", "snps,dw-pcie" for EP mode;

> 
>>>  - reg: Should contain the configuration address space.
>>>  - reg-names: Must be "config" for the PCIe configuration space.
>>>      (The old way of getting the configuration address space from "ranges"
>>> @@ -41,11 +42,11 @@ EP mode:
>>>  
>>>  Example configuration:
>>>  
>>> -	pcie: pcie@dffff000 {
>>> +	pcie: pcie@dfc00000 {
>>>  		compatible = "snps,dw-pcie";
>>> -		reg = <0xdffff000 0x1000>, /* Controller registers */
>>> -		      <0xd0000000 0x2000>; /* PCI config space */
>>> -		reg-names = "ctrlreg", "config";
>>> +		reg = <0xdfc00000 0x302000>, /* IP registers */
>>
>> which version of synopsys IP is this. I think the ideal thing to do here is to
>> have a separate register space for iATU.
> 
> I also agree with that. The unroll iATU was introduced on Synopsys IP version
> 4.80 and the kernel patch was release on 2016-08-10
> https://patchwork.ozlabs.org/patch/657796/
> However a separate register space for iATU implies some extra code do handle it
> (and of course some tests) that don't fit into this patch series, in my point of
> view. Can this task enter in the backlog in order to be done in another patch
> series?

Yes sure. I think we should also make sure existing binding doesn't break.

Thanks
Kishon

  reply	other threads:[~2018-04-03 10:57 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-28 11:38 [PATCH 0/8] Designware EP support and code clenan up Gustavo Pimentel
2018-03-28 11:38 ` [PATCH 1/8] bindings: PCI: designware: Example update Gustavo Pimentel
2018-04-02  5:23   ` Kishon Vijay Abraham I
2018-04-03 10:33     ` Gustavo Pimentel
2018-04-03 10:52       ` Kishon Vijay Abraham I [this message]
2018-04-03 10:53         ` Kishon Vijay Abraham I
2018-04-03 13:13           ` Gustavo Pimentel
2018-04-06  6:23             ` Kishon Vijay Abraham I
2018-03-28 11:38 ` [PATCH 2/8] PCI: dwc: designware: Add support for endpoint mode Gustavo Pimentel
2018-04-02  5:34   ` Kishon Vijay Abraham I
2018-04-04 10:20     ` Gustavo Pimentel
2018-04-06  7:16       ` Kishon Vijay Abraham I
2018-03-28 11:38 ` [PATCH 3/8] bindings: PCI: designware: Add support for the EP in designware driver Gustavo Pimentel
2018-04-02  5:35   ` Kishon Vijay Abraham I
2018-04-03 10:43     ` Gustavo Pimentel
2018-04-03 10:55       ` Kishon Vijay Abraham I
2018-04-03 13:20         ` Gustavo Pimentel
2018-04-06  7:04           ` Kishon Vijay Abraham I
2018-04-04 11:50   ` Lorenzo Pieralisi
2018-04-04 11:56     ` Gustavo Pimentel
2018-04-09 19:12   ` Rob Herring
2018-04-10 11:11     ` Gustavo Pimentel
2018-03-28 11:38 ` [PATCH 4/8] misc: pci_endpoint_test: Add designware EP entry Gustavo Pimentel
2018-04-02  5:36   ` Kishon Vijay Abraham I
2018-04-03 10:11     ` Gustavo Pimentel
2018-04-03 10:56       ` Kishon Vijay Abraham I
2018-03-28 11:38 ` [PATCH 5/8] PCI: dwc: designware: Define maximum number of vectors Gustavo Pimentel
2018-03-28 11:38 ` [PATCH 6/8] PCI: dwc: Replace lower into upper case characters Gustavo Pimentel
2018-03-28 12:05   ` Fabio Estevam
2018-03-28 13:00     ` Gustavo Pimentel
2018-03-29 13:56       ` Fabio Estevam
2018-03-28 11:38 ` [PATCH 7/8] PCI: dwc: Small computation improvement Gustavo Pimentel
2018-03-28 11:38 ` [PATCH 8/8] PCI: dwc: Replace magic number by defines Gustavo Pimentel

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