From: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
To: Steven Rostedt <rostedt@goodmis.org>
Cc: <arnd@arndb.de>, <catalin.marinas@arm.com>,
<gregkh@linuxfoundation.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<maz@kernel.org>, <quic_psodagud@quicinc.com>,
<quic_tsoni@quicinc.com>, <will@kernel.org>,
Prasad Sodagudi <psodagud@codeaurora.org>
Subject: Re: [PATCHv14 5/9] lib: Add register read/write tracing support
Date: Wed, 18 May 2022 20:48:14 +0530 [thread overview]
Message-ID: <c696ebfc-9a2a-7b12-7297-3be8a31a82d3@quicinc.com> (raw)
In-Reply-To: <20220518100721.18fb5876@gandalf.local.home>
Hi Steve,
On 5/18/2022 7:37 PM, Steven Rostedt wrote:
> On Wed, 4 May 2022 16:58:24 +0530
> Sai Prakash Ranjan <quic_saipraka@quicinc.com> wrote:
>
>> +#include <linux/tracepoint.h>
>> +
>> +DECLARE_EVENT_CLASS(rwmmio_rw_template,
>> +
>> + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
>> +
>> + TP_ARGS(caller, val, width, addr),
>> +
>> + TP_STRUCT__entry(
>> + __field(unsigned long, caller)
>> + __field(unsigned long, addr)
>> + __field(u64, val)
>> + __field(u8, width)
>> + ),
>> +
>> + TP_fast_assign(
>> + __entry->caller = caller;
>> + __entry->val = val;
>> + __entry->addr = (unsigned long)(void *)addr;
>> + __entry->width = width;
>> + ),
>> +
>> + TP_printk("%pS width=%d val=%#llx addr=%#lx",
>> + (void *)(unsigned long)__entry->caller, __entry->width,
> __entry->caller is already defined as "unsigned long", why the extra
> typecast?
I remember seeing compilation errors without this change in early versions of
the series. Let me check this again.
>> + __entry->val, __entry->addr)
>> +);
>> +
>> +DEFINE_EVENT(rwmmio_rw_template, rwmmio_write,
>> + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
>> + TP_ARGS(caller, val, width, addr)
>> +);
>> +
>> +DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_write,
>> + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
>> + TP_ARGS(caller, val, width, addr)
>> +);
>> +
>> +TRACE_EVENT(rwmmio_read,
>> +
>> + TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr),
>> +
>> + TP_ARGS(caller, width, addr),
>> +
>> + TP_STRUCT__entry(
>> + __field(unsigned long, caller)
>> + __field(unsigned long, addr)
>> + __field(u8, width)
>> + ),
>> +
>> + TP_fast_assign(
>> + __entry->caller = caller;
>> + __entry->addr = (unsigned long)(void *)addr;
>> + __entry->width = width;
>> + ),
>> +
>> + TP_printk("%pS width=%d addr=%#lx",
>> + (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr)
>
> Same here.
Same as above.
>> +);
>> +
>> +TRACE_EVENT(rwmmio_post_read,
>> +
>> + TP_PROTO(unsigned long caller, u64 val, u8 width, const volatile void __iomem *addr),
>> +
>> + TP_ARGS(caller, val, width, addr),
>> +
>> + TP_STRUCT__entry(
>> + __field(unsigned long, caller)
>> + __field(unsigned long, addr)
>> + __field(u64, val)
>> + __field(u8, width)
>> + ),
>> +
>> + TP_fast_assign(
>> + __entry->caller = caller;
>> + __entry->val = val;
>> + __entry->addr = (unsigned long)(void *)addr;
>> + __entry->width = width;
>> + ),
>> +
>> + TP_printk("%pS width=%d val=%#llx addr=%#lx",
>> + (void *)(unsigned long)__entry->caller, __entry->width,
> And here.
Same as above.
>> + __entry->val, __entry->addr)
>> +);
>> +
>> +#endif /* _TRACE_RWMMIO_H */
>> +
>> +#include <trace/define_trace.h>
>> diff --git a/lib/Kconfig b/lib/Kconfig
>> index 087e06b4cdfd..5e2fd075724f 100644
>> --- a/lib/Kconfig
>> +++ b/lib/Kconfig
>> @@ -118,6 +118,13 @@ config INDIRECT_IOMEM_FALLBACK
>> mmio accesses when the IO memory address is not a registered
>> emulated region.
>>
>> +config TRACE_MMIO_ACCESS
>> + bool "Register read/write tracing"
>> + depends on TRACING && ARCH_HAVE_TRACE_MMIO_ACCESS
>> + help
>> + Create tracepoints for MMIO read/write operations. These trace events
>> + can be used for logging all MMIO read/write operations.
>> +
>> source "lib/crypto/Kconfig"
>>
>> config CRC_CCITT
>> diff --git a/lib/Makefile b/lib/Makefile
>> index 6b9ffc1bd1ee..3df7d24e65d2 100644
>> --- a/lib/Makefile
>> +++ b/lib/Makefile
>> @@ -151,6 +151,8 @@ lib-y += logic_pio.o
>>
>> lib-$(CONFIG_INDIRECT_IOMEM) += logic_iomem.o
>>
>> +obj-$(CONFIG_TRACE_MMIO_ACCESS) += trace_readwrite.o
>> +
>> obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o
>>
>> obj-$(CONFIG_BTREE) += btree.o
>> diff --git a/lib/trace_readwrite.c b/lib/trace_readwrite.c
>> new file mode 100644
>> index 000000000000..88637038b30c
>> --- /dev/null
>> +++ b/lib/trace_readwrite.c
>> @@ -0,0 +1,47 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Register read and write tracepoints
>> + *
>> + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <linux/ftrace.h>
>> +#include <linux/module.h>
>> +#include <asm-generic/io.h>
>> +
>> +#define CREATE_TRACE_POINTS
>> +#include <trace/events/rwmmio.h>
>> +
>> +#ifdef CONFIG_TRACE_MMIO_ACCESS
>> +void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
> Where's the header file that defines these functions? I would think it
> should be in this patch as well.
It is present in "include/asm-generic/io.h" which is already included above.
Thanks,
Sai
> -- Steve
>
>
>> + unsigned long caller_addr)
>> +{
>> + trace_rwmmio_write(caller_addr, val, width, addr);
>> +}
>> +EXPORT_SYMBOL_GPL(log_write_mmio);
>> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_write);
>> +
>> +void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
>> + unsigned long caller_addr)
>> +{
>> + trace_rwmmio_post_write(caller_addr, val, width, addr);
>> +}
>> +EXPORT_SYMBOL_GPL(log_post_write_mmio);
>> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_write);
>> +
>> +void log_read_mmio(u8 width, const volatile void __iomem *addr,
>> + unsigned long caller_addr)
>> +{
>> + trace_rwmmio_read(caller_addr, width, addr);
>> +}
>> +EXPORT_SYMBOL_GPL(log_read_mmio);
>> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_read);
>> +
>> +void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
>> + unsigned long caller_addr)
>> +{
>> + trace_rwmmio_post_read(caller_addr, val, width, addr);
>> +}
>> +EXPORT_SYMBOL_GPL(log_post_read_mmio);
>> +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_read);
>> +#endif /* CONFIG_TRACE_MMIO_ACCESS */
next prev parent reply other threads:[~2022-05-18 15:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-04 11:28 [PATCHv14 0/9] lib/rwmmio/arm64: Add support to trace register reads/writes Sai Prakash Ranjan
2022-05-04 11:28 ` [PATCHv14 1/9] arm64: io: Use asm-generic high level MMIO accessors Sai Prakash Ranjan
2022-05-04 11:28 ` [PATCHv14 2/9] coresight: etm4x: Use asm-generic IO memory barriers Sai Prakash Ranjan
2022-05-05 23:44 ` Suzuki K Poulose
2022-05-06 3:02 ` Sai Prakash Ranjan
2022-05-06 9:21 ` Suzuki K Poulose
2022-05-06 13:22 ` Sai Prakash Ranjan
2022-05-04 11:28 ` [PATCHv14 3/9] irqchip/tegra: Fix overflow implicit truncation warnings Sai Prakash Ranjan
2022-05-04 11:28 ` [PATCHv14 4/9] drm/meson: " Sai Prakash Ranjan
2022-05-04 11:28 ` [PATCHv14 5/9] lib: Add register read/write tracing support Sai Prakash Ranjan
2022-05-11 3:51 ` Sai Prakash Ranjan
2022-05-17 6:41 ` Sai Prakash Ranjan
2022-05-18 14:07 ` Steven Rostedt
2022-05-18 15:18 ` Sai Prakash Ranjan [this message]
2022-05-18 16:45 ` Sai Prakash Ranjan
2022-05-04 11:28 ` [PATCHv14 6/9] KVM: arm64: Add a flag to disable MMIO trace for nVHE KVM Sai Prakash Ranjan
2022-05-04 11:28 ` [PATCHv14 7/9] asm-generic/io: Add logging support for MMIO accessors Sai Prakash Ranjan
2022-05-04 11:28 ` [PATCHv14 8/9] serial: qcom_geni_serial: Disable MMIO tracing for geni serial Sai Prakash Ranjan
2022-05-04 11:28 ` [PATCHv14 9/9] soc: qcom: geni: Disable MMIO tracing for GENI SE Sai Prakash Ranjan
2022-05-04 11:32 ` [PATCHv14 0/9] lib/rwmmio/arm64: Add support to trace register reads/writes Sai Prakash Ranjan
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