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From: "Christian König" <christian.koenig@amd.com>
To: Daniel Stone <daniel@fooishbar.org>,
	Nicolas Dufresne <nicolas@ndufresne.ca>
Cc: Daniel Vetter <daniel@ffwll.ch>,
	"Sharma, Shashank" <Shashank.Sharma@amd.com>,
	lkml <linux-kernel@vger.kernel.org>,
	dri-devel <dri-devel@lists.freedesktop.org>,
	linaro-mm-sig@lists.linaro.org,
	Sumit Semwal <sumit.semwal@linaro.org>,
	linux-media <linux-media@vger.kernel.org>
Subject: Re: DMA-buf and uncached system memory
Date: Thu, 23 Jun 2022 08:59:41 +0200	[thread overview]
Message-ID: <c6e65ee1-531e-d72c-a6a6-da7149e34f18@amd.com> (raw)
In-Reply-To: <CAPj87rPYQNkgVEdHECQcHcYe2nCpgF3RYQKk_=wwhvJSxwHXCg@mail.gmail.com>

Am 23.06.22 um 01:34 schrieb Daniel Stone:
> Hi Nicolas,
>
> On Wed, 22 Jun 2022 at 20:39, Nicolas Dufresne <nicolas@ndufresne.ca> wrote:
>> Le mardi 16 février 2021 à 10:25 +0100, Daniel Vetter a écrit :
>>> So I think if AMD also guarantees to drop clean cachelines just do the
>>> same thing we do right now for intel integrated + discrete amd, but in
>>> reserve. It's fragile, but it does work.
>> Sorry to disrupt, but if you pass V4L2 vmalloc data to Intel display driver, you
>> also get nice dirt on the screen. If you have a UVC webcam that produces a pixel
>> format compatible with your display, you can reproduce the issue quite easily
>> with:
>>
>>    gst-launch-1.0 v4l2src device=/dev/video0 ! kmssink
>>
>> p.s. some frame-rate are less likely to exhibit the issue, make sure you create
>> movement to see it.
> Right, this is because the UVC data in a vmalloc() area is not
> necessarily flushed from the CPU cache, and the importer expects it
> will be.

Yeah, but that is something perfectly valid for an exporter to do. So 
the bug is not in UVC.

>> The only solution I could think of (not implemented) was to detect in the
>> attach() call what the importers can do (with dev->coherent_dma_mask if I
>> recall), and otherwise flush the cache immediately and start flushing the cache
>> from now on signalling it for DQBUF (in vb2 workqueue or dqbuf ioctl, I don't
>> have an idea yet). I bet this idea is inapplicable to were you have fences, we
>> don't have that in v4l2.
>>
>> This idea was hinted by Robert Becket (now in CC), but perhaps I picked it up
>> wrong, explaining it wrong, etc. I'm no expert, just noticed there wasn't really
>> a good plan for that, so one needs to make one up. I'm not aware oh an importer
>> could know how the memory was allocated by the exporter, and worst, how an
>> importer could figure-out that the export is going to produce buffer with hot
>> CPU cache (UVC driver does memcpy from USB chunks of variable size to produce a
>> fixed size image).
> This is exactly what Christian was saying above.

Well more or less.

The exporter isn't doing anything wrong here. DMA-buf are supposed to be 
CPU cached and can also be cache hot.

The importer needs to be able to deal with that. Either by flushing the 
CPU cache manually (awkward), rejecting the DMA-buf for this use case 
(display scanout) or working around that inside it's driver (extra copy, 
different hw settings, etc...).

Regards,
Christian.

>
> Cheers,
> Daniel


  reply	other threads:[~2022-06-23  7:00 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-15  8:58 Christian König
2021-02-15  9:06 ` Simon Ser
2021-02-15  9:34   ` Christian König
2021-02-15 11:53     ` Lucas Stach
2021-02-15 12:04       ` Christian König
2021-02-15 12:16         ` Lucas Stach
2021-02-15 12:25           ` Christian König
2021-02-15 14:41         ` David Laight
2021-02-15 14:54           ` [Linaro-mm-sig] " Christian König
2021-02-15  9:49 ` Thomas Zimmermann
2021-02-15 12:00   ` Thomas Zimmermann
2021-02-15 12:10     ` Christian König
2021-02-15 20:46       ` Nicolas Dufresne
2021-02-15 20:39 ` Nicolas Dufresne
     [not found]   ` <5822b325-766e-ce3c-50eb-d7f54f14fd0b@mediatek.com>
     [not found]     ` <39f7f41a-af8d-4700-37da-9401455afb98@amd.com>
2022-06-21 15:42       ` Nicolas Dufresne
2022-06-22  9:05         ` [Linaro-mm-sig] " Christian König
2021-02-16  9:25 ` Daniel Vetter
2022-06-22 19:39   ` Nicolas Dufresne
2022-06-22 23:34     ` Daniel Stone
2022-06-23  6:59       ` Christian König [this message]
2022-06-23  7:13         ` Pekka Paalanen
2022-06-23  7:26           ` Christian König
2022-06-23  8:04             ` Lucas Stach
2022-06-23  8:14               ` Christian König
2022-06-23  8:58                 ` Lucas Stach
2022-06-23  9:09                   ` Christian König
2022-06-23  9:33                     ` Lucas Stach
2022-06-23  9:46                       ` Christian König
2022-06-23 10:13                         ` Lucas Stach
2022-06-23 11:10                           ` Christian König
2022-06-23 11:27                             ` Daniel Stone
2022-06-23 11:32                               ` Christian König
2022-06-24 22:02                                 ` [Linaro-mm-sig] " Daniel Vetter
2022-07-04 13:48                                   ` Christian König
2022-08-09 14:46                                     ` Daniel Vetter
2022-08-10  5:55                                       ` Christian König
2022-06-23 11:29                             ` Lucas Stach
2022-06-23 11:54                               ` Christian König
2022-06-23 12:14                                 ` Lucas Stach
2022-06-23 12:52                                   ` Christian König
2022-06-23 15:26                                     ` Lucas Stach
2022-06-24  6:54                                       ` Christian König
2022-06-24  8:10                                         ` Lucas Stach
2022-06-27 13:54                       ` Nicolas Dufresne
2022-06-27 14:06                         ` Lucas Stach
2022-06-27 14:30                           ` Nicolas Dufresne
2022-06-27 13:51                   ` Nicolas Dufresne
2022-06-23  8:13 ` Thomas Zimmermann
2022-06-23  8:26   ` Christian König
2022-06-23  8:42     ` Thomas Zimmermann
2022-08-09 15:01 ` Rob Clark

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