From: Nicolas Dufresne <nicolas@ndufresne.ca>
To: "Christian König" <christian.koenig@amd.com>,
linux-media <linux-media@vger.kernel.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
linaro-mm-sig@lists.linaro.org,
lkml <linux-kernel@vger.kernel.org>
Cc: Sumit Semwal <sumit.semwal@linaro.org>,
Daniel Vetter <daniel@ffwll.ch>,
"Sharma, Shashank" <Shashank.Sharma@amd.com>
Subject: Re: DMA-buf and uncached system memory
Date: Mon, 15 Feb 2021 15:39:25 -0500 [thread overview]
Message-ID: <cdb508e49eb1439f4e4c327d2a6738f219e04bf8.camel@ndufresne.ca> (raw)
In-Reply-To: <91ff0bbb-ea3a-2663-3453-dea96ccd6dd8@amd.com>
Le lundi 15 février 2021 à 09:58 +0100, Christian König a écrit :
> Hi guys,
>
> we are currently working an Freesync and direct scan out from system
> memory on AMD APUs in A+A laptops.
>
> On problem we stumbled over is that our display hardware needs to scan
> out from uncached system memory and we currently don't have a way to
> communicate that through DMA-buf.
>
> For our specific use case at hand we are going to implement something
> driver specific, but the question is should we have something more
> generic for this?
Hopefully I'm getting this right, but this makes me think of a long standing
issue I've met with Intel DRM and UVC driver. If I let the UVC driver allocate
the buffer, and import the resulting DMABuf (cacheable memory written with a cpu
copy in the kernel) into DRM, we can see cache artifact being displayed. While
if I use the DRM driver memory (dumb buffer in that case) it's clean because
there is a driver specific solution to that.
There is no obvious way for userspace application to know what's is right/wrong
way and in fact it feels like the kernel could solve this somehow without having
to inform userspace (perhaps).
>
> After all the system memory access pattern is a PCIe extension and as
> such something generic.
>
> Regards,
> Christian.
next prev parent reply other threads:[~2021-02-15 20:40 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-15 8:58 Christian König
2021-02-15 9:06 ` Simon Ser
2021-02-15 9:34 ` Christian König
2021-02-15 11:53 ` Lucas Stach
2021-02-15 12:04 ` Christian König
2021-02-15 12:16 ` Lucas Stach
2021-02-15 12:25 ` Christian König
2021-02-15 14:41 ` David Laight
2021-02-15 14:54 ` [Linaro-mm-sig] " Christian König
2021-02-15 9:49 ` Thomas Zimmermann
2021-02-15 12:00 ` Thomas Zimmermann
2021-02-15 12:10 ` Christian König
2021-02-15 20:46 ` Nicolas Dufresne
2021-02-15 20:39 ` Nicolas Dufresne [this message]
[not found] ` <5822b325-766e-ce3c-50eb-d7f54f14fd0b@mediatek.com>
[not found] ` <39f7f41a-af8d-4700-37da-9401455afb98@amd.com>
2022-06-21 15:42 ` Nicolas Dufresne
2022-06-22 9:05 ` [Linaro-mm-sig] " Christian König
2021-02-16 9:25 ` Daniel Vetter
2022-06-22 19:39 ` Nicolas Dufresne
2022-06-22 23:34 ` Daniel Stone
2022-06-23 6:59 ` Christian König
2022-06-23 7:13 ` Pekka Paalanen
2022-06-23 7:26 ` Christian König
2022-06-23 8:04 ` Lucas Stach
2022-06-23 8:14 ` Christian König
2022-06-23 8:58 ` Lucas Stach
2022-06-23 9:09 ` Christian König
2022-06-23 9:33 ` Lucas Stach
2022-06-23 9:46 ` Christian König
2022-06-23 10:13 ` Lucas Stach
2022-06-23 11:10 ` Christian König
2022-06-23 11:27 ` Daniel Stone
2022-06-23 11:32 ` Christian König
2022-06-24 22:02 ` [Linaro-mm-sig] " Daniel Vetter
2022-07-04 13:48 ` Christian König
2022-08-09 14:46 ` Daniel Vetter
2022-08-10 5:55 ` Christian König
2022-06-23 11:29 ` Lucas Stach
2022-06-23 11:54 ` Christian König
2022-06-23 12:14 ` Lucas Stach
2022-06-23 12:52 ` Christian König
2022-06-23 15:26 ` Lucas Stach
2022-06-24 6:54 ` Christian König
2022-06-24 8:10 ` Lucas Stach
2022-06-27 13:54 ` Nicolas Dufresne
2022-06-27 14:06 ` Lucas Stach
2022-06-27 14:30 ` Nicolas Dufresne
2022-06-27 13:51 ` Nicolas Dufresne
2022-06-23 8:13 ` Thomas Zimmermann
2022-06-23 8:26 ` Christian König
2022-06-23 8:42 ` Thomas Zimmermann
2022-08-09 15:01 ` Rob Clark
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