Re: [PATCH v5 04/10] drm/msm/mdp5: flush the interface before starting the timing engine

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 10/24/26 1:25 AM, Dmitry Baryshkov wrote:
> Disabling a CRTC and then enabling it again can produce an SMMU fault on
> MSM8996 as soon as the timing engine restarts, e.g. when fbcon takes over
> after kms_atomic:
> 
>   arm-smmu d00000.iommu: Unhandled context fault: fsr=0x402, iova=0x01fa6e00
> 
> The faulting address is inside the framebuffer that was scanned out
> before the disable, which has been released since. The pipes keep that
> address latched (CURRENT_SRC0_ADDR still points to the released buffer)
> because the plane removal flushed after the timing engine stopped never
> takes effect. On the next enable the pipes are programmed and flushed
> before the encoder is enabled, but that flush doesn't include the
> interface: the encoder enables the timing engine first and only then
> flushes the INTF. The first frame is fetched with the latched pipe
> configuration, from the released buffer.
> 
> Flush the interface before enabling the timing engine, the order used by
> both the DPU driver and the downstream mdss driver. With the INTF flush
> pending, the whole pending flush takes effect when the timing engine
> starts and the first frame is fetched with the new configuration.
> 
> Fixes: 06c0dd96bfbb ("drm/msm: add mdp5/apq8x74")
> Assisted-by: LLM
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad