* [PATCH] spi: fsl-dspi: Set max_speed_hz for master
@ 2016-03-21 20:11 Bhuvanchandra DV
2016-03-23 6:35 ` Stefan Agner
0 siblings, 1 reply; 2+ messages in thread
From: Bhuvanchandra DV @ 2016-03-21 20:11 UTC (permalink / raw)
To: broonie, shawnguo, kernel
Cc: stefan, haikun.wang, han.xu, linux-spi, linux-kernel, Bhuvanchandra DV
Calculate and update max speed from bus clock for SoC's
using DSPI IP.
The bus clock factor's are taken from the data sheet's
of respective SoC's.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
---
drivers/spi/spi-fsl-dspi.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 59a1143..8753276 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -121,18 +121,22 @@ enum dspi_trans_mode {
struct fsl_dspi_devtype_data {
enum dspi_trans_mode trans_mode;
+ u8 max_clock_factor;
};
static const struct fsl_dspi_devtype_data vf610_data = {
.trans_mode = DSPI_EOQ_MODE,
+ .max_clock_factor = 2,
};
static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
.trans_mode = DSPI_TCFQ_MODE,
+ .max_clock_factor = 8,
};
static const struct fsl_dspi_devtype_data ls2085a_data = {
.trans_mode = DSPI_TCFQ_MODE,
+ .max_clock_factor = 8,
};
struct fsl_dspi {
@@ -726,6 +730,9 @@ static int dspi_probe(struct platform_device *pdev)
}
clk_prepare_enable(dspi->clk);
+ master->max_speed_hz =
+ clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
+
init_waitqueue_head(&dspi->waitq);
platform_set_drvdata(pdev, master);
--
2.7.3
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] spi: fsl-dspi: Set max_speed_hz for master
2016-03-21 20:11 [PATCH] spi: fsl-dspi: Set max_speed_hz for master Bhuvanchandra DV
@ 2016-03-23 6:35 ` Stefan Agner
0 siblings, 0 replies; 2+ messages in thread
From: Stefan Agner @ 2016-03-23 6:35 UTC (permalink / raw)
To: Bhuvanchandra DV
Cc: broonie, shawnguo, kernel, haikun.wang, han.xu, linux-spi, linux-kernel
On 2016-03-21 13:11, Bhuvanchandra DV wrote:
> Calculate and update max speed from bus clock for SoC's
> using DSPI IP.
>
> The bus clock factor's are taken from the data sheet's
> of respective SoC's.
Plurals are without apostrophe...
I wonder if GCC optimizes this to a bit shift...
Acked-by: Stefan Agner <stefan@agner.ch>
>
> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> ---
> drivers/spi/spi-fsl-dspi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
> index 59a1143..8753276 100644
> --- a/drivers/spi/spi-fsl-dspi.c
> +++ b/drivers/spi/spi-fsl-dspi.c
> @@ -121,18 +121,22 @@ enum dspi_trans_mode {
>
> struct fsl_dspi_devtype_data {
> enum dspi_trans_mode trans_mode;
> + u8 max_clock_factor;
> };
>
> static const struct fsl_dspi_devtype_data vf610_data = {
> .trans_mode = DSPI_EOQ_MODE,
> + .max_clock_factor = 2,
> };
>
> static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
> .trans_mode = DSPI_TCFQ_MODE,
> + .max_clock_factor = 8,
> };
>
> static const struct fsl_dspi_devtype_data ls2085a_data = {
> .trans_mode = DSPI_TCFQ_MODE,
> + .max_clock_factor = 8,
> };
>
> struct fsl_dspi {
> @@ -726,6 +730,9 @@ static int dspi_probe(struct platform_device *pdev)
> }
> clk_prepare_enable(dspi->clk);
>
> + master->max_speed_hz =
> + clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
> +
> init_waitqueue_head(&dspi->waitq);
> platform_set_drvdata(pdev, master);
^ permalink raw reply [flat|nested] 2+ messages in thread
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2016-03-23 6:35 ` Stefan Agner
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