From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Abel Vesa <abel.vesa@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Subject: Re: [PATCH 2/3] arm64: dts: qcom: Introduce Eliza Soc base dtsi
Date: Tue, 10 Mar 2026 14:36:03 +0100 [thread overview]
Message-ID: <c883cc2f-f9e2-4b2a-a716-b6ad916bc004@oss.qualcomm.com> (raw)
In-Reply-To: <1e58955c-3e79-4503-8670-85e689bf8acb@kernel.org>
On 3/6/26 10:02 AM, Krzysztof Kozlowski wrote:
> On 24/02/2026 14:06, Konrad Dybcio wrote:
>> On 2/24/26 1:13 PM, Abel Vesa wrote:
>>> Introduce the initial support for the Qualcomm Eliza SoC.
>>> It is a high-tier SoC designed for mobile platforms.
>>>
>>> The initial submission enables support for:
>>> - CPU nodes with cpufreq and cpuidle support
>>> - Global Clock Controller (GCC)
>>> - Resource State Coordinator (RSC) with clock controller & genpd provider
>>> - Interrupt controller
>>> - Power Domain Controller (PDC)
>>> - Vendor specific SMMU
>>> - SPMI bus arbiter
>>> - Top Control and Status Register (TCSR)
>>> - Top Level Mode Multiplexer (TLMM)
>>> - Debug UART
>>> - Reserved memory nodes
>>> - Interconnect providers
>>> - System timer
>>> - UFS
>>>
>>> Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> + cpu-map {
>>> + cluster0 {
>>> + core0 {
>>> + cpu = <&cpu0>;
>>
>> The values of the MPIDR register (also present in 'reg' of CPU nodes)
>> suggest all these CPUs form a single logical cluster
>
> For reference:
>
> Data presented by firmware lies and different, e.g. fixed, firmware will
> give you different results. All resources I found (several of them -
> multiple docs, Block diagram from datasheet) say these are separate
> clusters, so this is the topology we should be using currently.
FWIW we discussed *MIDR*_EL1 (i.e. ""CPU ID"") with regards to the firmware
lying. M*P*IDR represents the position of the core within the topology, and
many, many recent Arm platforms have been reporting a single big cluster
because of:
https://developer.arm.com/documentation/100453/0401/The-DynamIQ-Shared-Unit/About-the-DSU
We tended to agree with that and you'll notice almost all recent platforms
have all the cores in a single cluster. I don't know if it was the right
decision, I believe all these years no one cared to check/benchmark the
impact that makes (if any)
Konrad
next prev parent reply other threads:[~2026-03-10 13:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-24 12:13 [PATCH 0/3] arm64: dts: qcom: Add base support for Eliza SoC and its MTP board Abel Vesa
2026-02-24 12:13 ` [PATCH 1/3] dt-bindings: arm: qcom: Document Eliza " Abel Vesa
2026-02-25 10:55 ` Krzysztof Kozlowski
2026-02-24 12:13 ` [PATCH 2/3] arm64: dts: qcom: Introduce Eliza Soc base dtsi Abel Vesa
2026-02-24 13:06 ` Konrad Dybcio
2026-02-24 13:11 ` Krzysztof Kozlowski
2026-03-06 9:02 ` Krzysztof Kozlowski
2026-03-10 13:36 ` Konrad Dybcio [this message]
2026-03-12 12:19 ` Abel Vesa
2026-02-24 15:23 ` Dmitry Baryshkov
2026-02-24 12:13 ` [PATCH 3/3] arm64: dts: qcom: eliza: Enable Eliza MTP board support Abel Vesa
2026-02-24 13:09 ` Konrad Dybcio
2026-03-12 12:22 ` Abel Vesa
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