From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: geert+renesas@glider.be, mturquette@baylibre.com,
sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, alexandre.belloni@bootlin.com,
magnus.damm@gmail.com, p.zabel@pengutronix.de,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH v4 03/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
Date: Mon, 21 Oct 2024 10:47:03 +0300 [thread overview]
Message-ID: <c8f3a1b5-e823-4508-a9e0-721c8ca1210a@tuxon.dev> (raw)
In-Reply-To: <m4kxv7cba6qd67ahhh4cal6sgieohgow6f3tdvqoxvheemtp4j@gpxbkxd3tvat>
On 21.10.2024 10:32, Krzysztof Kozlowski wrote:
> On Sat, Oct 19, 2024 at 11:47:29AM +0300, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
>> the tamper detector and a small general usage memory of 128B.
>>
>> The VBATTB controller controls the clock for the RTC on the Renesas
>> RZ/G3S. The HW block diagram for the clock logic is as follows:
>>
>> +----------+ XC `\
>> RTXIN --->| |----->| \ +----+ VBATTCLK
>> | 32K clock| | |----->|gate|----------->
>> | osc | XBYP | | +----+
>
> Messed indent. Switch to spaces.
>
>> RTXOUT --->| |----->| /
>> +----------+ ,/
>>
>> One could connect as input to this HW block either a crystal or
>> an external clock device.
>>
>> After discussions w/ Stephen Boyd the clock tree associated with this
>> hardware block was exported in Linux as:
>>
>> input-xtal
>> xbyp
>> xc
>> mux
>> vbattclk
>>
>> where:
>> - input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
>> - xc, xbyp are mux inputs
>> - mux is the internal mux
>> - vbattclk is the gate clock that feeds in the end the RTC
>>
>> to allow selecting the input of the MUX though assigned-clock DT
>> properties, using the already existing clock drivers and avoid adding
>> other DT properties.
>>
>> This allows select the input of the mux based on the type of the
>> connected input clock:
>> - if the 32768 crystal is connected as input for the VBATTB,
>> the input of the mux should be xc
>> - if an external clock device is connected as input for the VBATTB the
>> input of the mux should be xbyp
>
>> + clocks:
>> + items:
>> + - description: VBATTB module clock
>> + - description: RTC input clock (crystal or external clock device)
>> +
>> + clock-names:
>> + items:
>> + - const: bclk
>> + - const: rtx
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + resets:
>> + items:
>> + - description: VBATTB module reset
>> +
>> + quartz-load-femtofarads:
>> + description: load capacitance of the on board crystal
>> + enum: [ 4000, 7000, 9000, 12500 ]
>
> It's not required, so:
> default: ?
OK, I'll add the default.
>
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - interrupts
>> + - clocks
>> + - clock-names
>> + - '#clock-cells'
>> + - power-domains
>> + - resets
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/r9a08g045-cpg.h>
>> + #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> + clock-controller@1005c000 {
>> + compatible = "renesas,r9a08g045-vbattb";
>> + reg = <0x1005c000 0x1000>;
>> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
>> + clock-names = "bclk", "rtx";
>> + assigned-clocks = <&vbattb VBATTB_MUX>;
>> + assigned-clock-parents = <&vbattb VBATTB_XC>;
>
> Why are you configuring internal clocks to internal parents? That's part
> internal to this device, not DTS... or at least some explanation would
> be useful.
>
> Best regards,
> Krzysztof
>
next prev parent reply other threads:[~2024-10-21 7:47 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-19 8:47 [PATCH v4 00/12] Add RTC support for the Renesas RZ/G3S SoC Claudiu
2024-10-19 8:47 ` [PATCH v4 01/12] dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC Claudiu
2024-10-21 7:28 ` Krzysztof Kozlowski
2024-10-24 14:19 ` Geert Uytterhoeven
2024-10-19 8:47 ` [PATCH v4 02/12] clk: renesas: r9a08g045: Add power domain " Claudiu
2024-10-24 14:19 ` Geert Uytterhoeven
2024-10-19 8:47 ` [PATCH v4 03/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Claudiu
2024-10-21 7:32 ` Krzysztof Kozlowski
2024-10-21 7:34 ` Krzysztof Kozlowski
2024-10-21 7:49 ` Claudiu Beznea
2024-10-21 7:47 ` Claudiu Beznea [this message]
2024-10-24 14:21 ` Geert Uytterhoeven
2024-10-19 8:47 ` [PATCH v4 04/12] clk: linux/clk-provider.h: Add devm_clk_hw_register_gate_parent_hw() Claudiu
2024-10-19 8:47 ` [PATCH v4 05/12] clk: renesas: clk-vbattb: Add VBATTB clock driver Claudiu
2024-10-24 14:21 ` Geert Uytterhoeven
2024-10-19 8:47 ` [PATCH v4 06/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Claudiu
2024-10-19 10:32 ` Rob Herring (Arm)
2024-10-19 8:47 ` [PATCH v4 07/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC Claudiu
2024-10-19 16:16 ` Uwe Kleine-König
2024-10-19 8:47 ` [PATCH v4 08/12] arm64: dts: renesas: r9a08g045: Add VBATTB node Claudiu
2024-10-24 14:22 ` Geert Uytterhoeven
2024-10-19 8:47 ` [PATCH v4 09/12] arm64: dts: renesas: r9a08g045: Add RTC node Claudiu
2024-10-24 14:22 ` Geert Uytterhoeven
2024-10-19 8:47 ` [PATCH v4 10/12] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB Claudiu
2024-10-24 14:22 ` Geert Uytterhoeven
2024-10-19 8:47 ` [PATCH v4 11/12] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC Claudiu
2024-10-19 8:47 ` [PATCH v4 12/12] arm64: defconfig: Enable VBATTB clock and Renesas RTCA-3 flags Claudiu
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