Re: [PATCH] dt-bindings: interrupt-controller: Add Xilinx INTC binding

[Michal Simek <michal.simek@amd.com>]

On 7/22/25 09:40, Krzysztof Kozlowski wrote:
> On Tue, Jul 22, 2025 at 08:49:42AM +0200, Michal Simek wrote:
>> +  "#interrupt-cells":
>> +    const: 2
>> +    description:
>> +      Specifies the number of cells needed to encode an interrupt source.
>> +      The value shall be a minimum of 1. The Xilinx device trees typically
>> +      use 2 but the 2nd value is not used.
>> +
>> +  interrupt-controller: true
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +    description:
>> +      Specifies the interrupt of the parent controller from which it is chained.
>> +
>> +  xlnx,kind-of-intr:
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    description:
>> +      A 32 bit value specifying the interrupt type for each possible interrupt
>> +      (1 = edge, 0 = level). The interrupt type typically comes in thru
>> +      the device tree node of the interrupt generating device, but in this case
>> +      the interrupt type is determined by the interrupt controller based on how
>> +      it was implemented.
> 
> enum: [ 0, 1 ]

It is hex value for all interrupts together.
And bit position correspond to interrupt line. And you can mix edge or level 
interrupts together and this is the property which distinguish them.

I know that separate cell is normally used but it has never been converted to be 
like that but interrupt-cells is 2 that binding allows using this description too.

Thanks,
Michal