Re: [PATCH] dt-bindings: interrupt-controller: Add Xilinx INTC binding

[Michal Simek <michal.simek@amd.com>]

On 7/22/25 09:17, Krzysztof Kozlowski wrote:
> On 22/07/2025 08:49, Michal Simek wrote:
>> Add description for AMD/Xilinx interrupt controller.
>> IP acts as primary interrupt controller on Microblaze systems or can be
>> used as secondary interrupt controller on ARM based systems like Zynq,
>> ZynqMP, Versal or Versal Gen 2. Also as secondary interrupt controller on
>> Microblaze-V (Risc-V) systems.
>>
>> Over the years IP exists in multiple variants based on attached bus as OPB,
>> PLB or AXI that's why generic filename is used.
>>
>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>> ---
>>
>> https://docs.amd.com/v/u/en-US/pg099-axi-intc
> 
> 
> We usually do not take bindings without users, that's why bindings patch
> is always part of some other patchset. Commit msg also did not clarify
> the usecase here (or exception).

Example DT is already the part of arch/microblaze/.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/microblaze/boot/dts/system.dts?h=v6.16-rc7#n338

DT has been added in 2014 before dt bindings that's why it was never documented.

Thanks,
Michal