* [PATCH 1/2] arm64: dts: socfpga: agilex5: Add L2 and L3 cache
@ 2025-10-15 2:12 adrianhoyin.ng
2025-10-15 2:12 ` [PATCH 2/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes adrianhoyin.ng
0 siblings, 1 reply; 3+ messages in thread
From: adrianhoyin.ng @ 2025-10-15 2:12 UTC (permalink / raw)
To: robh, dinguyen, krzk+dt, conor+dt, devicetree, linux-kernel
Cc: adrianhoyin.ng
From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Add L2 and L3 cache nodes to the device tree to resolve the
"unable to detect cache hierarchy" warning reported by cacheinfo.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 04e99cd7e74b..19f55a02bd56 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -37,6 +37,7 @@ cpu0: cpu@0 {
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@@ -44,6 +45,7 @@ cpu1: cpu@1 {
reg = <0x100>;
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@@ -51,6 +53,7 @@ cpu2: cpu@2 {
reg = <0x200>;
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@@ -58,7 +61,22 @@ cpu3: cpu@3 {
reg = <0x300>;
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&L2>;
};
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ next-level-cache = <&L3>;
+ cache-unified;
+ };
+
+ L3: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ };
+
};
psci {
--
2.49.GIT
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 2/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
2025-10-15 2:12 [PATCH 1/2] arm64: dts: socfpga: agilex5: Add L2 and L3 cache adrianhoyin.ng
@ 2025-10-15 2:12 ` adrianhoyin.ng
2025-11-04 21:19 ` Dinh Nguyen
0 siblings, 1 reply; 3+ messages in thread
From: adrianhoyin.ng @ 2025-10-15 2:12 UTC (permalink / raw)
To: robh, dinguyen, krzk+dt, conor+dt, devicetree, linux-kernel
Cc: adrianhoyin.ng
From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Add SMMU-V3 Performance Monitoring Counter Group (PMCG) nodes for
Agilex5 to support SMMU performance event monitoring.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 19f55a02bd56..633eab69e1c9 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -151,6 +151,12 @@ usbphy0: usbphy {
compatible = "usb-nop-xceiv";
};
+ pmu0: pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
soc: soc@0 {
compatible = "simple-bus";
ranges = <0 0 0 0xffffffff>;
@@ -840,5 +846,61 @@ queue7 {
};
};
};
+
+ pmu0_tcu: pmu@16002000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x16002000 0x1000>,
+ <0x16022000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu0: pmu@16042000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x16042000 0x1000>,
+ <0x16052000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu1: pmu@16062000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x16062000 0x1000>,
+ <0x16072000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu2: pmu@16082000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x16082000 0x1000>,
+ <0x16092000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu3: pmu@160a2000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x160A2000 0x1000>,
+ <0x160B2000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu4: pmu@160c2000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x160C2000 0x1000>,
+ <0x160D2000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu5: pmu@160e2000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x160E2000 0x1000>,
+ <0x160F2000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
+ };
};
};
--
2.49.GIT
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 2/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
2025-10-15 2:12 ` [PATCH 2/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes adrianhoyin.ng
@ 2025-11-04 21:19 ` Dinh Nguyen
0 siblings, 0 replies; 3+ messages in thread
From: Dinh Nguyen @ 2025-11-04 21:19 UTC (permalink / raw)
To: adrianhoyin.ng, robh, krzk+dt, conor+dt, devicetree, linux-kernel
On 10/14/25 21:12, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
>
> Add SMMU-V3 Performance Monitoring Counter Group (PMCG) nodes for
> Agilex5 to support SMMU performance event monitoring.
>
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
> .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 19f55a02bd56..633eab69e1c9 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -151,6 +151,12 @@ usbphy0: usbphy {
> compatible = "usb-nop-xceiv";
> };
>
> + pmu0: pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> soc: soc@0 {
> compatible = "simple-bus";
> ranges = <0 0 0 0xffffffff>;
> @@ -840,5 +846,61 @@ queue7 {
> };
> };
> };
> +
> + pmu0_tcu: pmu@16002000 {
> + compatible = "arm,smmu-v3-pmcg";
> + reg = <0x16002000 0x1000>,
> + <0x16022000 0x1000>;
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> + pmu0_tbu0: pmu@16042000 {
> + compatible = "arm,smmu-v3-pmcg";
> + reg = <0x16042000 0x1000>,
> + <0x16052000 0x1000>;
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> + pmu0_tbu1: pmu@16062000 {
> + compatible = "arm,smmu-v3-pmcg";
> + reg = <0x16062000 0x1000>,
> + <0x16072000 0x1000>;
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> + pmu0_tbu2: pmu@16082000 {
> + compatible = "arm,smmu-v3-pmcg";
> + reg = <0x16082000 0x1000>,
> + <0x16092000 0x1000>;
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> + pmu0_tbu3: pmu@160a2000 {
> + compatible = "arm,smmu-v3-pmcg";
> + reg = <0x160A2000 0x1000>,
> + <0x160B2000 0x1000>;
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> + pmu0_tbu4: pmu@160c2000 {
> + compatible = "arm,smmu-v3-pmcg";
> + reg = <0x160C2000 0x1000>,
> + <0x160D2000 0x1000>;
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
> + };
> +
> + pmu0_tbu5: pmu@160e2000 {
> + compatible = "arm,smmu-v3-pmcg";
> + reg = <0x160E2000 0x1000>,
> + <0x160F2000 0x1000>;
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
> + };
> };
> };
Applied!
Thanks,
Dinh
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-10-15 2:12 [PATCH 1/2] arm64: dts: socfpga: agilex5: Add L2 and L3 cache adrianhoyin.ng
2025-10-15 2:12 ` [PATCH 2/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes adrianhoyin.ng
2025-11-04 21:19 ` Dinh Nguyen
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