[PATCH v1] riscv: add hardware error trap handler support

[PATCH v1] riscv: add hardware error trap handler support

["$(name)" <$(mail address)>]

From: Rui Qi <qirui.001@bytedance.com>

adds support for handling hardware error traps (exception code 19)
in the RISC-V architecture. The changes include:

- Add do_trap_hardware_error function declaration in asm-prototypes.h
- Add hardware error trap vector entry in entry.S exception vector table
- Implement do_trap_hardware_error handler in traps.c that generates
  SIGBUS with BUS_MCEERR_AR for hardware errors

This enables proper handling of hardware error exceptions that may occur
in RISC-V systems, providing appropriate error reporting and signal
generation for user space processes.

Signed-off-by: Rui Qi <qirui.001@bytedance.com>
---
 arch/riscv/include/asm/asm-prototypes.h | 1 +
 arch/riscv/kernel/entry.S               | 1 +
 arch/riscv/kernel/traps.c               | 2 ++
 3 files changed, 4 insertions(+)

diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h
index 41ec5cdec367..5b90ba5314ee 100644
--- a/arch/riscv/include/asm/asm-prototypes.h
+++ b/arch/riscv/include/asm/asm-prototypes.h
@@ -40,6 +40,7 @@ asmlinkage void riscv_v_context_nesting_end(struct pt_regs *regs);
 #define DECLARE_DO_ERROR_INFO(name)	asmlinkage void name(struct pt_regs *regs)
 
 DECLARE_DO_ERROR_INFO(do_trap_unknown);
+DECLARE_DO_ERROR_INFO(do_trap_hardware_error);
 DECLARE_DO_ERROR_INFO(do_trap_insn_misaligned);
 DECLARE_DO_ERROR_INFO(do_trap_insn_fault);
 DECLARE_DO_ERROR_INFO(do_trap_insn_illegal);
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 60eb221296a6..d011fb51c59a 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -498,6 +498,7 @@ SYM_DATA_START_LOCAL(excp_vect_table)
 	RISCV_PTR do_trap_unknown /* cause=16 */
 	RISCV_PTR do_trap_unknown /* cause=17 */
 	RISCV_PTR do_trap_software_check /* cause=18 is sw check exception */
+	RISCV_PTR do_trap_hardware_error /* hardware error (19) */
 SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end)
 
 #ifndef CONFIG_MMU
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 5fb57fad188a..7cdb5b26d03d 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -165,6 +165,8 @@ asmlinkage __visible __trap_section void name(struct pt_regs *regs)		\
 
 DO_ERROR_INFO(do_trap_unknown,
 	SIGILL, ILL_ILLTRP, "unknown exception");
+DO_ERROR_INFO(do_trap_hardware_error,
+	SIGBUS, BUS_MCEERR_AR, "hardware error");
 DO_ERROR_INFO(do_trap_insn_misaligned,
 	SIGBUS, BUS_ADRALN, "instruction address misaligned");
 DO_ERROR_INFO(do_trap_insn_fault,
-- 
2.20.1

Re: [PATCH v1] riscv: add hardware error trap handler support

[Paul Walmsley]

Hi,

On Mon, 2 Feb 2026, "$(name)" <$(mail address)> wrote:

Looks like your mail user agent is broken - can you fix that, please?

> From: Rui Qi <qirui.001@bytedance.com>
> 
> adds support for handling hardware error traps (exception code 19)
> in the RISC-V architecture. The changes include:
> 
> - Add do_trap_hardware_error function declaration in asm-prototypes.h
> - Add hardware error trap vector entry in entry.S exception vector table
> - Implement do_trap_hardware_error handler in traps.c that generates
>   SIGBUS with BUS_MCEERR_AR for hardware errors
> 
> This enables proper handling of hardware error exceptions that may occur
> in RISC-V systems, providing appropriate error reporting and signal
> generation for user space processes.
> 
> Signed-off-by: Rui Qi <qirui.001@bytedance.com>

Thanks, queued for v7.1.


- Paul