[PATCH 1/2] arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells

[PATCH 1/2] arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells

[Krzysztof Kozlowski]

Add missing address-cells 0 to the PCI interrupt node to silence W=1
warning:

  uniphier-ld20.dtsi:941.4-944.29: Warning (interrupt_map): /soc@0/pcie@66000000:interrupt-map:
    Missing property '#address-cells' in node /soc@0/pcie@66000000/legacy-interrupt-controller, using 0 as fallback

Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
   the fourth component "parent unit address", which size is defined by
   '#address-cells' of the node pointed to by the interrupt-parent
   component, is not used (=0)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 335093da6573..875b93856a64 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -947,6 +947,7 @@ pcie: pcie@66000000 {
 
 			pcie_intc: legacy-interrupt-controller {
 				interrupt-controller;
+				#address-cells = <0>;
 				#interrupt-cells = <1>;
 				interrupt-parent = <&gic>;
 				interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.48.1

[PATCH 2/2] arm64: dts: socionext: uniphier-pxs3: Add default PCI interrup controller address cells

[Krzysztof Kozlowski]

Add missing address-cells 0 to the PCI interrupt node to silence W=1
warning:

  uniphier-pxs3.dtsi:915.4-918.29: Warning (interrupt_map): /soc@0/pcie@66000000:interrupt-map:
    Missing property '#address-cells' in node /soc@0/pcie@66000000/legacy-interrupt-controller, using 0 as fallback

Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
   the fourth component "parent unit address", which size is defined by
   '#address-cells' of the node pointed to by the interrupt-parent
   component, is not used (=0)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index d6e3cc6fdb25..4d6c3c2dbea6 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -921,6 +921,7 @@ pcie: pcie@66000000 {
 
 			pcie_intc: legacy-interrupt-controller {
 				interrupt-controller;
+				#address-cells = <0>;
 				#interrupt-cells = <1>;
 				interrupt-parent = <&gic>;
 				interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.48.1

Re: [PATCH 1/2] arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells

[Kunihiko Hayashi]

Hi Krzysztof,

On 2025/08/22 22:33, Krzysztof Kozlowski wrote:
> Add missing address-cells 0 to the PCI interrupt node to silence W=1
> warning:
> 
>    uniphier-ld20.dtsi:941.4-944.29: Warning (interrupt_map):
> /soc@0/pcie@66000000:interrupt-map:
>      Missing property '#address-cells' in node
> /soc@0/pcie@66000000/legacy-interrupt-controller, using 0 as fallback
> 
> Value '0' is correct because:
> 1. GIC interrupt controller does not have children,
> 2. interrupt-map property (in PCI node) consists of five components and
>     the fourth component "parent unit address", which size is defined by
>     '#address-cells' of the node pointed to by the interrupt-parent
>     component, is not used (=0)

I understand that "parent unit address" is omitted, and according to
the devicetree specification, "#address-cells" define the the size of
the address. However, GIC doesn't specify the address, so this line
is needed to indicate it.

For both patches,
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

There is no tree to manage the SoC-specified commits, so please apply
this series into the DT tree.

Thank you,

---
Best Regards
Kunihiko Hayashi

Re: [PATCH 1/2] arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells

[Krzysztof Kozlowski]

On Fri, 22 Aug 2025 15:33:19 +0200, Krzysztof Kozlowski wrote:
> Add missing address-cells 0 to the PCI interrupt node to silence W=1
> warning:
> 
>   uniphier-ld20.dtsi:941.4-944.29: Warning (interrupt_map): /soc@0/pcie@66000000:interrupt-map:
>     Missing property '#address-cells' in node /soc@0/pcie@66000000/legacy-interrupt-controller, using 0 as fallback
> 
> Value '0' is correct because:
> 1. GIC interrupt controller does not have children,
> 2. interrupt-map property (in PCI node) consists of five components and
>    the fourth component "parent unit address", which size is defined by
>    '#address-cells' of the node pointed to by the interrupt-parent
>    component, is not used (=0)
> 
> [...]

Applied, thanks!

[1/2] arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells
      https://git.kernel.org/krzk/linux-dt/c/613fb0c8bd49df4fb28bca89aa5363856487096f
[2/2] arm64: dts: socionext: uniphier-pxs3: Add default PCI interrup controller address cells
      https://git.kernel.org/krzk/linux-dt/c/a29bf0b10a1a7f51afb91c1ff9edd73b0ca1fd18

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>