From: Marc Zyngier <marc.zyngier@arm.com>
To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Rob Herring <robh+dt@kernel.org>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Kumar Gala <galak@codeaurora.org>, Andrew Lunn <andrew@lunn.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Gregory Clement <gregory.clement@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org,
Nadav Haklai <nadavh@marvell.com>,
Hanna Hawa <hannah@marvell.com>,
Yehuda Yitschak <yehuday@marvell.com>,
Antoine Tenart <antoine.tenart@free-electrons.com>
Subject: Re: [PATCH 0/6] Add support for the ICU unit in Marvell Armada 7K/8K
Date: Tue, 30 May 2017 15:15:54 +0100 [thread overview]
Message-ID: <cc93efea-84ea-970d-914a-141241b8cace@arm.com> (raw)
In-Reply-To: <1496135772-20694-1-git-send-email-thomas.petazzoni@free-electrons.com>
Hi Thomas,
On 30/05/17 10:16, Thomas Petazzoni wrote:
> Hello,
>
> The Marvell Armada 7K/8K SoCs are composed of two parts: the AP (which
> contains the CPU cores) and the CP (which contains most
> peripherals). The 7K SoCs have one CP, while the 8K SoCs have two CPs,
> doubling the number of available peripherals.
>
> In terms of interrupt handling, all devices in the CPs are connected
> through wired interrupt to a unit called ICU located in each CP. This
> unit converts the wired interrupts from the devices into memory
> transactions.
>
> Inside the AP, there is a GIC extension called GICP, which allows a
> memory write transaction to trigger a GIC SPI interrupt. The ICUs in
> each CP are therefore configured to trigger a memory write into the
> appropriate GICP register so that a wired interrupt from a CP device
> is converted into a memory write, itself converted into a regular GIC
> SPI interrupt.
>
> Until now, the configuration of the ICU was done statically by the
> firmware, and therefore the Device Tree files in Linux were specifying
> directly GIC interrupts for the interrupts of CP devices. However,
> with the growing number of devices in the CP, a static allocation
> scheme doesn't work for the long term.
>
> This patch series therefore makes Linux aware of the ICU: GIC SPI
> interrupts are dynamically allocated, and the ICU is configured
> accordingly to route a CP wired interrupt to the allocated GIC SPI
> interrupt.
>
> In detail:
>
> - The first two patches are the Device Tree binding patches
>
> - The third patch is a minimal driver for the GICP unit. All it does
> is clear interrupts that may have been left pending by the
> firmware.
>
> - The fourth patch is the most important done, which adds the driver
> for the ICU itself.
>
> - The fifth patch adjust Kconfig.platforms to select the GICP and ICU
> drivers.
>
> - The last patch adjusts the Device Tree files of the Armada 7K/8K to
> use the ICU.
For a first drop, this looks quite good, and the few comments I've had
should be pretty easy to address. Looking forward to reviewing v2.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
prev parent reply other threads:[~2017-05-30 14:16 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-30 9:16 Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 2/6] dt-bindings: interrupt-controller: add DT binding for the Marvell ICU Thomas Petazzoni
2017-05-30 10:37 ` Marc Zyngier
2017-05-30 11:41 ` Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 3/6] irqchip: irq-mvebu-gicp: new driver for Marvell GICP Thomas Petazzoni
2017-05-30 13:55 ` Marc Zyngier
2017-05-30 14:54 ` Thomas Petazzoni
2017-05-30 15:17 ` Marc Zyngier
2017-05-30 15:25 ` Thomas Petazzoni
2017-05-30 15:33 ` Marc Zyngier
2017-05-30 9:16 ` [PATCH 4/6] irqchip: irq-mvebu-icu: new driver for Marvell ICU Thomas Petazzoni
2017-05-30 11:10 ` Marc Zyngier
2017-05-30 12:05 ` Thomas Petazzoni
2017-05-30 13:06 ` Marc Zyngier
2017-05-30 13:17 ` Thomas Petazzoni
2017-05-30 13:40 ` Marc Zyngier
2017-06-25 6:47 ` [EXT] " Yehuda Yitschak
2017-05-30 12:04 ` Antoine Tenart
2017-05-30 12:19 ` Russell King - ARM Linux
2017-05-30 12:33 ` Thomas Petazzoni
2017-05-30 12:56 ` Russell King - ARM Linux
2017-05-30 13:27 ` Andrew Lunn
2017-05-30 13:34 ` Thomas Petazzoni
2017-05-30 13:42 ` Russell King - ARM Linux
2017-05-30 14:03 ` Andrew Lunn
2017-05-30 14:36 ` Russell King - ARM Linux
2017-05-30 14:26 ` Thomas Petazzoni
2017-05-30 14:39 ` Russell King - ARM Linux
2017-05-30 14:49 ` Andrew Lunn
2017-05-30 15:08 ` Russell King - ARM Linux
2017-05-30 13:28 ` Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 5/6] arm64: marvell: enable ICU and GICP drivers Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K Thomas Petazzoni
2017-05-30 14:02 ` Marc Zyngier
2017-05-30 14:28 ` Thomas Petazzoni
2017-05-30 9:16 ` [PATCH 6/6] arm64: dts: marvell: enable GICP and ICU Thomas Petazzoni
2017-05-30 9:22 ` Thomas Petazzoni
2017-05-30 14:15 ` Marc Zyngier [this message]
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