Re: [PATCH v2 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1

["Kumar, Udit" <u-kumar1@ti.com>]

Thanks Siddharth

On 4/22/2025 5:30 PM, Siddharth Vadapalli wrote:
> The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit
> address space of the respective PCIe Controllers. Hence, update the
> ranges to include them.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>
> Link to v1 patch:
> https://lore.kernel.org/r/20250417120407.2646929-4-s-vadapalli@ti.com/
> Changes since v1:
> - Fixed the 'ranges' to set the size as 4 GB instead of the incorrect
>    value of 128 MB.
>
> Regards,
> Siddharth.
>
>   arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> index a7f2f52f42f7..b6e22c242951 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> @@ -126,6 +126,8 @@ cbass_main: bus@100000 {
>   			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
>   			 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
>   			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
> +			 <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
> +			 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 *


Reviewed-by: Udit Kumar <u-kumar1@ti.com>


> /
>   			 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
>   			 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
>   			 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */