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From: "Colin King (gmail)" <colin.i.king@gmail.com>
To: Kevin Tang <kevin3.tang@gmail.com>
Cc: Kevin Tang <kevin.tang@unisoc.com>,
	Orson Zhai <orsonzhai@gmail.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: shift and mask issue in drivers/gpu/drm/sprd/megacores_pll.c
Date: Mon, 7 Oct 2024 10:46:50 +0100	[thread overview]
Message-ID: <cd76a15e-70e9-4abf-9932-38d520b66205@gmail.com> (raw)

Hi,

I noticed a shift/mask issue in dphy_set_pll_reg() in 
drivers/gpu/drm/sprd/megacores_pll.c, the expression (pll->kint << 4) & 
0xf is
always zero:

         ...
         reg_val[4] = pll->kint >> 12;
         reg_val[5] = pll->kint >> 4;
         reg_val[6] = pll->out_sel | ((pll->kint << 4) & 0xf);
         ...

I'm not sure what the correct expression should be, but the current 
assignment to reg_val[6] seems incorrect to me.

Colin






                 reply	other threads:[~2024-10-07  9:46 UTC|newest]

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