* shift and mask issue in drivers/gpu/drm/sprd/megacores_pll.c
@ 2024-10-07 9:46 Colin King (gmail)
0 siblings, 0 replies; only message in thread
From: Colin King (gmail) @ 2024-10-07 9:46 UTC (permalink / raw)
To: Kevin Tang
Cc: Kevin Tang, Orson Zhai, Maarten Lankhorst, dri-devel, linux-kernel
Hi,
I noticed a shift/mask issue in dphy_set_pll_reg() in
drivers/gpu/drm/sprd/megacores_pll.c, the expression (pll->kint << 4) &
0xf is
always zero:
...
reg_val[4] = pll->kint >> 12;
reg_val[5] = pll->kint >> 4;
reg_val[6] = pll->out_sel | ((pll->kint << 4) & 0xf);
...
I'm not sure what the correct expression should be, but the current
assignment to reg_val[6] seems incorrect to me.
Colin
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