* Re: kvm_intel fails to load on Conroe CPUs running Linux 4.12 [not found] <35eda6a9-086e-f899-e131-288f2346effe@wiesinger.com> @ 2017-08-17 21:14 ` Gerhard Wiesinger 2017-08-27 7:47 ` [Qemu-devel] " Gerhard Wiesinger 0 siblings, 1 reply; 13+ messages in thread From: Gerhard Wiesinger @ 2017-08-17 21:14 UTC (permalink / raw) To: linux-kernel, Paolo Bonzini, qemu-devel On 17.08.2017 22:58, Gerhard Wiesinger wrote: > > On 07.08.2017 19:50, Paolo Bonzini wrote: > > >Not much to say, unfortunately. It's pretty much the same capabilities > >as a Prescott/Cedar Mill processor, except that it has MSR bitmaps. It > >also lacks FlexPriority compared to the Conroe I had checked. > > > >It's not great that even the revert patch doesn't apply cleanly---this > >is *not* necessarily a boring area of the hypervisor... > > > >Given the rarity of your machine I'm currently leaning towards _not_ > >reverting the change. I'll check another non-Xeon Core 2 tomorrow that > >is from December 2008 (IIRC). If that one also lacks vNMI, or if I get > >other reports, I suppose I will have to reconsider that. Hello Paolo, Can you please revert the patch. CPU is a Core 2 Extreme QX6700: SL9UL (B3) running VERY stable with ECC RAM for years now. https://ark.intel.com/products/28028/Intel-Core2-Extreme-Processor-QX6700-8M-Cache-2_66-GHz-1066-MHz-FSB?q=Core%202%20Extreme%20QX6700 https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors CPU details below. Thank you. Ciao, Gerhard cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Core(TM)2 Quad CPU @ 2.66GHz stepping : 7 microcode : 0x6a cpu MHz : 1596.000 cache size : 4096 KB physical id : 0 siblings : 4 core id : 0 cpu cores : 4 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 10 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lahf_lm tpr_shadow dtherm bugs : bogomips : 5333.45 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: Script output: Basic VMX Information Hex: 0x1a040000000007 Revision 7 VMCS size 1024 VMCS restricted to 32 bit addresses no Dual-monitor support yes VMCS memory type 6 INS/OUTS instruction information no IA32_VMX_TRUE_*_CTLS support no pin-based controls External interrupt exiting yes NMI exiting yes Virtual NMIs no Activate VMX-preemption timer no Process posted interrupts no primary processor-based controls Interrupt window exiting yes Use TSC offsetting yes HLT exiting yes INVLPG exiting yes MWAIT exiting yes RDPMC exiting yes RDTSC exiting yes CR3-load exiting forced CR3-store exiting forced CR8-load exiting yes CR8-store exiting yes Use TPR shadow yes NMI-window exiting no MOV-DR exiting yes Unconditional I/O exiting yes Use I/O bitmaps yes Monitor trap flag no Use MSR bitmaps yes MONITOR exiting yes PAUSE exiting yes Activate secondary control no secondary processor-based controls Virtualize APIC accesses no Enable EPT no Descriptor-table exiting no Enable RDTSCP no Virtualize x2APIC mode no Enable VPID no WBINVD exiting no Unrestricted guest no APIC register emulation no Virtual interrupt delivery no PAUSE-loop exiting no RDRAND exiting no Enable INVPCID no Enable VM functions no VMCS shadowing no Enable ENCLS exiting no RDSEED exiting no Enable PML no EPT-violation #VE no Conceal non-root operation from PT no Enable XSAVES/XRSTORS no Mode-based execute control (XS/XU) no TSC scaling no VM-Exit controls Save debug controls forced Host address-space size yes Load IA32_PERF_GLOBAL_CTRL no Acknowledge interrupt on exit yes Save IA32_PAT no Load IA32_PAT no Save IA32_EFER no Load IA32_EFER no Save VMX-preemption timer value no Clear IA32_BNDCFGS no Conceal VM exits from PT no VM-Entry controls Load debug controls forced IA-32e mode guest yes Entry to SMM yes Deactivate dual-monitor treatment yes Load IA32_PERF_GLOBAL_CTRL no Load IA32_PAT no Load IA32_EFER no Load IA32_BNDCFGS no Conceal VM entries from PT no Miscellaneous data Hex: 0x403c0 VMX-preemption timer scale (log2) 0 Store EFER.LMA into IA-32e mode guest control no HLT activity state yes Shutdown activity state yes Wait-for-SIPI activity state yes IA32_SMBASE support no Number of CR3-target values 4 MSR-load/store count recommendation 0 IA32_SMM_MONITOR_CTL[2] can be set to 1 no VMWRITE to VM-exit information fields no Inject event with insn length=0 no MSEG revision identifier 0 VPID and EPT capabilities Hex: 0x0 Execute-only EPT translations no Page-walk length 4 no Paging-structure memory type UC no Paging-structure memory type WB no 2MB EPT pages no 1GB EPT pages no INVEPT supported no EPT accessed and dirty flags no Single-context INVEPT no All-context INVEPT no INVVPID supported no Individual-address INVVPID no Single-context INVVPID no All-context INVVPID no Single-context-retaining-globals INVVPID no VM Functions Hex: 0x0 EPTP Switching no ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] kvm_intel fails to load on Conroe CPUs running Linux 4.12 2017-08-17 21:14 ` kvm_intel fails to load on Conroe CPUs running Linux 4.12 Gerhard Wiesinger @ 2017-08-27 7:47 ` Gerhard Wiesinger [not found] ` <CABgObfYzngJPgS9agXMrRENVD_e+3Hm=y+KD5dp9na8jNwuumw@mail.gmail.com> 0 siblings, 1 reply; 13+ messages in thread From: Gerhard Wiesinger @ 2017-08-27 7:47 UTC (permalink / raw) To: linux-kernel, Paolo Bonzini, qemu-devel On 17.08.2017 23:14, Gerhard Wiesinger wrote: > On 17.08.2017 22:58, Gerhard Wiesinger wrote: > > > > On 07.08.2017 19:50, Paolo Bonzini wrote: > > > > >Not much to say, unfortunately. It's pretty much the same capabilities > > >as a Prescott/Cedar Mill processor, except that it has MSR bitmaps. It > > >also lacks FlexPriority compared to the Conroe I had checked. > > > > > >It's not great that even the revert patch doesn't apply cleanly---this > > >is *not* necessarily a boring area of the hypervisor... > > > > > >Given the rarity of your machine I'm currently leaning towards _not_ > > >reverting the change. I'll check another non-Xeon Core 2 tomorrow that > > >is from December 2008 (IIRC). If that one also lacks vNMI, or if I get > > >other reports, I suppose I will have to reconsider that. > > Hello Paolo, > > Can you please revert the patch. > > CPU is a Core 2 Extreme QX6700: SL9UL (B3) running VERY stable with > ECC RAM for years now. > https://ark.intel.com/products/28028/Intel-Core2-Extreme-Processor-QX6700-8M-Cache-2_66-GHz-1066-MHz-FSB?q=Core%202%20Extreme%20QX6700 > > https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors > > CPU details below. > > Thank you. > > Ciao, > Gerhard Hello Paolo, Any update on this major issue? Thnx. Ciao, Gerhard ^ permalink raw reply [flat|nested] 13+ messages in thread
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* Re: [Qemu-devel] kvm_intel fails to load on Conroe CPUs running Linux 4.12 [not found] ` <CABgObfZFwJMpU_D8SMkuiEhb0qBokHL0jpwmuzdE73TReHMFkg@mail.gmail.com> @ 2017-08-27 14:59 ` Gerhard Wiesinger [not found] ` <0e69cbad-f658-03be-0191-1b6fe588147b@wiesinger.com> 1 sibling, 0 replies; 13+ messages in thread From: Gerhard Wiesinger @ 2017-08-27 14:59 UTC (permalink / raw) To: Paolo Bonzini; +Cc: Kernel Mailing List, Linux, qemu-devel On 27.08.2017 14:03, Paolo Bonzini wrote: > Il 27 ago 2017 9:49 AM, "Gerhard Wiesinger" <lists@wiesinger.com> ha > scritto: > > On 17.08.2017 23:14, Gerhard Wiesinger wrote: > >> On 17.08.2017 22:58, Gerhard Wiesinger wrote: >>> On 07.08.2017 19:50, Paolo Bonzini wrote: >>> >>>> Not much to say, unfortunately. It's pretty much the same capabilities >>>> as a Prescott/Cedar Mill processor, except that it has MSR bitmaps. It >>>> also lacks FlexPriority compared to the Conroe I had checked. >>>> >>>> It's not great that even the revert patch doesn't apply cleanly---this >>>> is *not* necessarily a boring area of the hypervisor... >>>> >>>> Given the rarity of your machine I'm currently leaning towards _not_ >>>> reverting the change. I'll check another non-Xeon Core 2 tomorrow that >>>> is from December 2008 (IIRC). If that one also lacks vNMI, or if I get >>>> other reports, I suppose I will have to reconsider that. >> Hello Paolo, >> >> Can you please revert the patch. >> >> CPU is a Core 2 Extreme QX6700: SL9UL (B3) running VERY stable with ECC >> RAM for years now. >> https://ark.intel.com/products/28028/Intel-Core2-Extreme- >> Processor-QX6700-8M-Cache-2_66-GHz-1066-MHz-FSB?q=Core% >> 202%20Extreme%20QX6700 >> https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors >> >> CPU details below. >> >> Thank you. >> >> Ciao, >> Gerhard >> > Hello Paolo, > > Any update on this major issue? > > > We will revert the patch, but 4.13.0 will not have the fix. Expect it in > later stable kernels (because vacations). Thnx. Why will 4.13.0 NOT have the fix? Thnx. Ciao, Gerhard ^ permalink raw reply [flat|nested] 13+ messages in thread
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* Re: [Qemu-devel] kvm_intel fails to load on Conroe CPUs running Linux 4.12 [not found] ` <1b37b04c-349f-28f7-fb6c-fbbbe8415b33@wiesinger.com> @ 2017-09-15 17:07 ` Paolo Bonzini 2017-09-27 19:31 ` Gerhard Wiesinger 0 siblings, 1 reply; 13+ messages in thread From: Paolo Bonzini @ 2017-09-15 17:07 UTC (permalink / raw) To: Gerhard Wiesinger; +Cc: qemu-devel, Kernel Mailing List, Linux On 15/09/2017 16:43, Gerhard Wiesinger wrote: > On 27.08.2017 20:55, Paolo Bonzini wrote: >> >> >> Il 27 ago 2017 4:48 PM, "Gerhard Wiesinger" <lists@wiesinger.com >> <mailto:lists@wiesinger.com>> ha scritto: >> >> On 27.08.2017 14 <tel:27.08.2017%2014>:03, Paolo Bonzini wrote: >> >> >> We will revert the patch, but 4.13.0 will not have the fix. >> Expect it in later stable kernels (because vacations). >> >> >> Thnx. Why will 4.13.0 NOT have the fix? >> >> >> Because maintainers are on vacation! :-) >> >> > > Hello Paolo, > > Any update on this for 4.12 and 4.13 kernels? A late fix is better than a wrong fix. Hope to get to it next week! Paolo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] kvm_intel fails to load on Conroe CPUs running Linux 4.12 2017-09-15 17:07 ` Paolo Bonzini @ 2017-09-27 19:31 ` Gerhard Wiesinger 0 siblings, 0 replies; 13+ messages in thread From: Gerhard Wiesinger @ 2017-09-27 19:31 UTC (permalink / raw) To: Paolo Bonzini; +Cc: qemu-devel, Kernel Mailing List, Linux On 15.09.2017 19:07, Paolo Bonzini wrote: > On 15/09/2017 16:43, Gerhard Wiesinger wrote: >> On 27.08.2017 20:55, Paolo Bonzini wrote: >>> >>> Il 27 ago 2017 4:48 PM, "Gerhard Wiesinger" <lists@wiesinger.com >>> <mailto:lists@wiesinger.com>> ha scritto: >>> >>> On 27.08.2017 14 <tel:27.08.2017%2014>:03, Paolo Bonzini wrote: >>> >>> >>> We will revert the patch, but 4.13.0 will not have the fix. >>> Expect it in later stable kernels (because vacations). >>> >>> >>> Thnx. Why will 4.13.0 NOT have the fix? >>> >>> >>> Because maintainers are on vacation! :-) >>> >>> >> Hello Paolo, >> >> Any update on this for 4.12 and 4.13 kernels? > A late fix is better than a wrong fix. Hope to get to it next week! Hello Paolo, Any update? Thnx. Ciao, Gerhard ^ permalink raw reply [flat|nested] 13+ messages in thread
* kvm_intel fails to load on Conroe CPUs running Linux 4.12
@ 2017-08-05 19:26 Sebastian Rachuj
2017-08-06 21:10 ` Paolo Bonzini
0 siblings, 1 reply; 13+ messages in thread
From: Sebastian Rachuj @ 2017-08-05 19:26 UTC (permalink / raw)
To: pbonzini, rkrcmar, tglx, mingo, hpa, x86, kvm, linux-kernel
Dear linux developers,
since my upgrade from linux 4.11 to linux 4.12 the "kvm_intel" module does not load correctly anymore. "Modprobing" the kernel module gives an Input/Output error. It seems to be related to the CPU architecture and (to my knowledge) affects Conroe CPUs. I did a bisect and found the following commit as the guilty one:
commit 2c82878b0cb38fd516fd612c67852a6bbf282003
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: Mon Mar 27 14:37:28 2017 +0200
KVM: VMX: require virtual NMI support
Virtual NMIs are only missing in Prescott and Yonah chips. Both are obsolete
for virtualization usage---Yonah is 32-bit only even---so drop vNMI emulation.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Since the commit message only mentions Prescott and Yonah chips, I wanted to ask whether this commit is also intended to affect Conroe CPUs (which are probably still a bit more widespread). Do you see a solution to bring back support for Conroe chips?
Thank you for your hard work on the kernel!
Best regards,
Sebastian Rachuj
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: kvm_intel fails to load on Conroe CPUs running Linux 4.12 2017-08-05 19:26 Sebastian Rachuj @ 2017-08-06 21:10 ` Paolo Bonzini 2017-08-06 21:23 ` Sebastian Rachuj 0 siblings, 1 reply; 13+ messages in thread From: Paolo Bonzini @ 2017-08-06 21:10 UTC (permalink / raw) To: Sebastian Rachuj, rkrcmar, tglx, mingo, hpa, x86, kvm, linux-kernel On 05/08/2017 21:26, Sebastian Rachuj wrote: > Dear linux developers, > > since my upgrade from linux 4.11 to linux 4.12 the "kvm_intel" module > does not load correctly anymore. "Modprobing" the kernel module gives an > Input/Output error. It seems to be related to the CPU architecture and > (to my knowledge) affects Conroe CPUs. I did a bisect and found the > following commit as the guilty one: What is your cpuinfo? I tested on a Conroe Xeon X3220 (family 6, model 15, stepping 11) when I posted that patch, and it did have virtual NMIs. Paolo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: kvm_intel fails to load on Conroe CPUs running Linux 4.12 2017-08-06 21:10 ` Paolo Bonzini @ 2017-08-06 21:23 ` Sebastian Rachuj 2017-08-07 9:43 ` Paolo Bonzini 0 siblings, 1 reply; 13+ messages in thread From: Sebastian Rachuj @ 2017-08-06 21:23 UTC (permalink / raw) To: Paolo Bonzini, rkrcmar, tglx, mingo, hpa, x86, kvm, linux-kernel On 06.08.2017 23:10, Paolo Bonzini wrote: > On 05/08/2017 21:26, Sebastian Rachuj wrote: >> Dear linux developers, >> >> since my upgrade from linux 4.11 to linux 4.12 the "kvm_intel" module >> does not load correctly anymore. "Modprobing" the kernel module gives an >> Input/Output error. It seems to be related to the CPU architecture and >> (to my knowledge) affects Conroe CPUs. I did a bisect and found the >> following commit as the guilty one: > > What is your cpuinfo? I tested on a Conroe Xeon X3220 (family 6, > model 15, stepping 11) when I posted that patch, and it did have virtual > NMIs. Thank you for looking into the issue. My cpuinfo is as follows: $ cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Core(TM)2 CPU 6420 @ 2.13GHz stepping : 6 microcode : 0xc6 cpu MHz : 2128.000 cache size : 4096 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 2 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 10 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lahf_lm tpr_shadow dtherm bugs : bogomips : 4275.23 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: processor : 1 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Core(TM)2 CPU 6420 @ 2.13GHz stepping : 6 microcode : 0xc6 cpu MHz : 2128.000 cache size : 4096 KB physical id : 0 siblings : 2 core id : 1 cpu cores : 2 apicid : 1 initial apicid : 1 fpu : yes fpu_exception : yes cpuid level : 10 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lahf_lm tpr_shadow dtherm bugs : bogomips : 4275.05 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: kvm_intel fails to load on Conroe CPUs running Linux 4.12 2017-08-06 21:23 ` Sebastian Rachuj @ 2017-08-07 9:43 ` Paolo Bonzini 2017-08-07 17:12 ` Nadav Amit 2017-08-07 17:17 ` Sebastian Rachuj 0 siblings, 2 replies; 13+ messages in thread From: Paolo Bonzini @ 2017-08-07 9:43 UTC (permalink / raw) To: Sebastian Rachuj, rkrcmar, tglx, mingo, hpa, x86, kvm, linux-kernel [-- Attachment #1: Type: text/plain, Size: 2845 bytes --] On 06/08/2017 23:23, Sebastian Rachuj wrote: > On 06.08.2017 23:10, Paolo Bonzini wrote: >> On 05/08/2017 21:26, Sebastian Rachuj wrote: >>> Dear linux developers, >>> >>> since my upgrade from linux 4.11 to linux 4.12 the "kvm_intel" module >>> does not load correctly anymore. "Modprobing" the kernel module gives an >>> Input/Output error. It seems to be related to the CPU architecture and >>> (to my knowledge) affects Conroe CPUs. I did a bisect and found the >>> following commit as the guilty one: >> >> What is your cpuinfo? I tested on a Conroe Xeon X3220 (family 6, >> model 15, stepping 11) when I posted that patch, and it did have virtual >> NMIs. > > Thank you for looking into the issue. My cpuinfo is as follows: Looks like Intel was already differentiating virtualization features across SKUs. Please run the attached script as root to see what other things are different (apparently) between non-Xeon and Xeon Conroes. Thanks, Paolo > $ cat /proc/cpuinfo > processor : 0 > vendor_id : GenuineIntel > cpu family : 6 > model : 15 > model name : Intel(R) Core(TM)2 CPU 6420 @ 2.13GHz > stepping : 6 > microcode : 0xc6 > cpu MHz : 2128.000 > cache size : 4096 KB > physical id : 0 > siblings : 2 > core id : 0 > cpu cores : 2 > apicid : 0 > initial apicid : 0 > fpu : yes > fpu_exception : yes > cpuid level : 10 > wp : yes > flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca > cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall > nx lm constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf > pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lahf_lm > tpr_shadow dtherm > bugs : > bogomips : 4275.23 > clflush size : 64 > cache_alignment : 64 > address sizes : 36 bits physical, 48 bits virtual > power management: > > processor : 1 > vendor_id : GenuineIntel > cpu family : 6 > model : 15 > model name : Intel(R) Core(TM)2 CPU 6420 @ 2.13GHz > stepping : 6 > microcode : 0xc6 > cpu MHz : 2128.000 > cache size : 4096 KB > physical id : 0 > siblings : 2 > core id : 1 > cpu cores : 2 > apicid : 1 > initial apicid : 1 > fpu : yes > fpu_exception : yes > cpuid level : 10 > wp : yes > flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca > cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall > nx lm constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf > pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lahf_lm > tpr_shadow dtherm > bugs : > bogomips : 4275.05 > clflush size : 64 > cache_alignment : 64 > address sizes : 36 bits physical, 48 bits virtual > power management: [-- Attachment #2: vmxcap --] [-- Type: text/plain, Size: 8741 bytes --] #!/usr/bin/python # # tool for querying VMX capabilities # # Copyright 2009-2010 Red Hat, Inc. # # Authors: # Avi Kivity <avi@redhat.com> # # This work is licensed under the terms of the GNU GPL, version 2. See # the COPYING file in the top-level directory. MSR_IA32_VMX_BASIC = 0x480 MSR_IA32_VMX_PINBASED_CTLS = 0x481 MSR_IA32_VMX_PROCBASED_CTLS = 0x482 MSR_IA32_VMX_EXIT_CTLS = 0x483 MSR_IA32_VMX_ENTRY_CTLS = 0x484 MSR_IA32_VMX_MISC_CTLS = 0x485 MSR_IA32_VMX_PROCBASED_CTLS2 = 0x48B MSR_IA32_VMX_EPT_VPID_CAP = 0x48C MSR_IA32_VMX_TRUE_PINBASED_CTLS = 0x48D MSR_IA32_VMX_TRUE_PROCBASED_CTLS = 0x48E MSR_IA32_VMX_TRUE_EXIT_CTLS = 0x48F MSR_IA32_VMX_TRUE_ENTRY_CTLS = 0x490 MSR_IA32_VMX_VMFUNC = 0x491 class msr(object): def __init__(self): try: self.f = open('/dev/cpu/0/msr', 'rb', 0) except: self.f = open('/dev/msr0', 'rb', 0) def read(self, index, default = None): import struct self.f.seek(index) try: return struct.unpack('Q', self.f.read(8))[0] except: return default class Control(object): def __init__(self, name, bits, cap_msr, true_cap_msr = None): self.name = name self.bits = bits self.cap_msr = cap_msr self.true_cap_msr = true_cap_msr def read2(self, nr): m = msr() val = m.read(nr, 0) return (val & 0xffffffff, val >> 32) def show(self): print(self.name) mbz, mb1 = self.read2(self.cap_msr) tmbz, tmb1 = 0, 0 if self.true_cap_msr: tmbz, tmb1 = self.read2(self.true_cap_msr) for bit in sorted(self.bits.keys()): zero = not (mbz & (1 << bit)) one = mb1 & (1 << bit) true_zero = not (tmbz & (1 << bit)) true_one = tmb1 & (1 << bit) s= '?' if (self.true_cap_msr and true_zero and true_one and one and not zero): s = 'default' elif zero and not one: s = 'no' elif one and not zero: s = 'forced' elif one and zero: s = 'yes' print(' %-40s %s' % (self.bits[bit], s)) class Misc(object): def __init__(self, name, bits, msr): self.name = name self.bits = bits self.msr = msr def show(self): print(self.name) value = msr().read(self.msr, 0) print(' Hex: 0x%x' % (value)) def first_bit(key): if type(key) is tuple: return key[0] else: return key for bits in sorted(self.bits.keys(), key = first_bit): if type(bits) is tuple: lo, hi = bits fmt = int else: lo = hi = bits def fmt(x): return { True: 'yes', False: 'no' }[x] v = (value >> lo) & ((1 << (hi - lo + 1)) - 1) print(' %-40s %s' % (self.bits[bits], fmt(v))) controls = [ Misc( name = 'Basic VMX Information', bits = { (0, 30): 'Revision', (32,44): 'VMCS size', 48: 'VMCS restricted to 32 bit addresses', 49: 'Dual-monitor support', (50, 53): 'VMCS memory type', 54: 'INS/OUTS instruction information', 55: 'IA32_VMX_TRUE_*_CTLS support', }, msr = MSR_IA32_VMX_BASIC, ), Control( name = 'pin-based controls', bits = { 0: 'External interrupt exiting', 3: 'NMI exiting', 5: 'Virtual NMIs', 6: 'Activate VMX-preemption timer', 7: 'Process posted interrupts', }, cap_msr = MSR_IA32_VMX_PINBASED_CTLS, true_cap_msr = MSR_IA32_VMX_TRUE_PINBASED_CTLS, ), Control( name = 'primary processor-based controls', bits = { 2: 'Interrupt window exiting', 3: 'Use TSC offsetting', 7: 'HLT exiting', 9: 'INVLPG exiting', 10: 'MWAIT exiting', 11: 'RDPMC exiting', 12: 'RDTSC exiting', 15: 'CR3-load exiting', 16: 'CR3-store exiting', 19: 'CR8-load exiting', 20: 'CR8-store exiting', 21: 'Use TPR shadow', 22: 'NMI-window exiting', 23: 'MOV-DR exiting', 24: 'Unconditional I/O exiting', 25: 'Use I/O bitmaps', 27: 'Monitor trap flag', 28: 'Use MSR bitmaps', 29: 'MONITOR exiting', 30: 'PAUSE exiting', 31: 'Activate secondary control', }, cap_msr = MSR_IA32_VMX_PROCBASED_CTLS, true_cap_msr = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, ), Control( name = 'secondary processor-based controls', bits = { 0: 'Virtualize APIC accesses', 1: 'Enable EPT', 2: 'Descriptor-table exiting', 3: 'Enable RDTSCP', 4: 'Virtualize x2APIC mode', 5: 'Enable VPID', 6: 'WBINVD exiting', 7: 'Unrestricted guest', 8: 'APIC register emulation', 9: 'Virtual interrupt delivery', 10: 'PAUSE-loop exiting', 11: 'RDRAND exiting', 12: 'Enable INVPCID', 13: 'Enable VM functions', 14: 'VMCS shadowing', 15: 'Enable ENCLS exiting', 16: 'RDSEED exiting', 17: 'Enable PML', 18: 'EPT-violation #VE', 19: 'Conceal non-root operation from PT', 20: 'Enable XSAVES/XRSTORS', 22: 'Mode-based execute control (XS/XU)', 25: 'TSC scaling', }, cap_msr = MSR_IA32_VMX_PROCBASED_CTLS2, ), Control( name = 'VM-Exit controls', bits = { 2: 'Save debug controls', 9: 'Host address-space size', 12: 'Load IA32_PERF_GLOBAL_CTRL', 15: 'Acknowledge interrupt on exit', 18: 'Save IA32_PAT', 19: 'Load IA32_PAT', 20: 'Save IA32_EFER', 21: 'Load IA32_EFER', 22: 'Save VMX-preemption timer value', 23: 'Clear IA32_BNDCFGS', 24: 'Conceal VM exits from PT', }, cap_msr = MSR_IA32_VMX_EXIT_CTLS, true_cap_msr = MSR_IA32_VMX_TRUE_EXIT_CTLS, ), Control( name = 'VM-Entry controls', bits = { 2: 'Load debug controls', 9: 'IA-32e mode guest', 10: 'Entry to SMM', 11: 'Deactivate dual-monitor treatment', 13: 'Load IA32_PERF_GLOBAL_CTRL', 14: 'Load IA32_PAT', 15: 'Load IA32_EFER', 16: 'Load IA32_BNDCFGS', 17: 'Conceal VM entries from PT', }, cap_msr = MSR_IA32_VMX_ENTRY_CTLS, true_cap_msr = MSR_IA32_VMX_TRUE_ENTRY_CTLS, ), Misc( name = 'Miscellaneous data', bits = { (0,4): 'VMX-preemption timer scale (log2)', 5: 'Store EFER.LMA into IA-32e mode guest control', 6: 'HLT activity state', 7: 'Shutdown activity state', 8: 'Wait-for-SIPI activity state', 15: 'IA32_SMBASE support', (16,24): 'Number of CR3-target values', (25,27): 'MSR-load/store count recommendation', 28: 'IA32_SMM_MONITOR_CTL[2] can be set to 1', 29: 'VMWRITE to VM-exit information fields', 30: 'Inject event with insn length=0', (32,63): 'MSEG revision identifier', }, msr = MSR_IA32_VMX_MISC_CTLS, ), Misc( name = 'VPID and EPT capabilities', bits = { 0: 'Execute-only EPT translations', 6: 'Page-walk length 4', 8: 'Paging-structure memory type UC', 14: 'Paging-structure memory type WB', 16: '2MB EPT pages', 17: '1GB EPT pages', 20: 'INVEPT supported', 21: 'EPT accessed and dirty flags', 25: 'Single-context INVEPT', 26: 'All-context INVEPT', 32: 'INVVPID supported', 40: 'Individual-address INVVPID', 41: 'Single-context INVVPID', 42: 'All-context INVVPID', 43: 'Single-context-retaining-globals INVVPID', }, msr = MSR_IA32_VMX_EPT_VPID_CAP, ), Misc( name = 'VM Functions', bits = { 0: 'EPTP Switching', }, msr = MSR_IA32_VMX_VMFUNC, ), ] for c in controls: c.show() ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: kvm_intel fails to load on Conroe CPUs running Linux 4.12 2017-08-07 9:43 ` Paolo Bonzini @ 2017-08-07 17:12 ` Nadav Amit 2017-08-07 17:17 ` Sebastian Rachuj 1 sibling, 0 replies; 13+ messages in thread From: Nadav Amit @ 2017-08-07 17:12 UTC (permalink / raw) To: Paolo Bonzini Cc: Sebastian Rachuj, rkrcmar, tglx, mingo, hpa, x86, kvm, linux-kernel Paolo Bonzini <pbonzini@redhat.com> wrote: > On 06/08/2017 23:23, Sebastian Rachuj wrote: >> On 06.08.2017 23:10, Paolo Bonzini wrote: >>> On 05/08/2017 21:26, Sebastian Rachuj wrote: >>>> Dear linux developers, >>>> >>>> since my upgrade from linux 4.11 to linux 4.12 the "kvm_intel" module >>>> does not load correctly anymore. "Modprobing" the kernel module gives an >>>> Input/Output error. It seems to be related to the CPU architecture and >>>> (to my knowledge) affects Conroe CPUs. I did a bisect and found the >>>> following commit as the guilty one: >>> >>> What is your cpuinfo? I tested on a Conroe Xeon X3220 (family 6, >>> model 15, stepping 11) when I posted that patch, and it did have virtual >>> NMIs. >> >> Thank you for looking into the issue. My cpuinfo is as follows: > > Looks like Intel was already differentiating virtualization features > across SKUs. Please run the attached script as root to see what other > things are different (apparently) between non-Xeon and Xeon Conroes. There may be another explanation. If I remember correctly from my days in Intel, Intel initially sold CMWA (Conroe) B-step. The next step, E-step, introduced a couple of new features, which may have included vNMI. The CPU of Sebastian appears to be B1 according to cpuinfo. Nadav ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: kvm_intel fails to load on Conroe CPUs running Linux 4.12 2017-08-07 9:43 ` Paolo Bonzini 2017-08-07 17:12 ` Nadav Amit @ 2017-08-07 17:17 ` Sebastian Rachuj 2017-08-07 17:50 ` Paolo Bonzini 1 sibling, 1 reply; 13+ messages in thread From: Sebastian Rachuj @ 2017-08-07 17:17 UTC (permalink / raw) To: Paolo Bonzini, rkrcmar, tglx, mingo, hpa, x86, kvm, linux-kernel On 07.08.2017 11:43, Paolo Bonzini wrote: > On 06/08/2017 23:23, Sebastian Rachuj wrote: >> On 06.08.2017 23:10, Paolo Bonzini wrote: >>> On 05/08/2017 21:26, Sebastian Rachuj wrote: >>>> Dear linux developers, >>>> >>>> since my upgrade from linux 4.11 to linux 4.12 the "kvm_intel" module >>>> does not load correctly anymore. "Modprobing" the kernel module gives an >>>> Input/Output error. It seems to be related to the CPU architecture and >>>> (to my knowledge) affects Conroe CPUs. I did a bisect and found the >>>> following commit as the guilty one: >>> >>> What is your cpuinfo? I tested on a Conroe Xeon X3220 (family 6, >>> model 15, stepping 11) when I posted that patch, and it did have virtual >>> NMIs. >> >> Thank you for looking into the issue. My cpuinfo is as follows: > > Looks like Intel was already differentiating virtualization features > across SKUs. Please run the attached script as root to see what other > things are different (apparently) between non-Xeon and Xeon Conroes. Here you are, I hope it helps: # python vmxcap Basic VMX Information Hex: 0x1a040000000007 Revision 7 VMCS size 1024 VMCS restricted to 32 bit addresses no Dual-monitor support yes VMCS memory type 6 INS/OUTS instruction information no IA32_VMX_TRUE_*_CTLS support no pin-based controls External interrupt exiting yes NMI exiting yes Virtual NMIs no Activate VMX-preemption timer no Process posted interrupts no primary processor-based controls Interrupt window exiting yes Use TSC offsetting yes HLT exiting yes INVLPG exiting yes MWAIT exiting yes RDPMC exiting yes RDTSC exiting yes CR3-load exiting forced CR3-store exiting forced CR8-load exiting yes CR8-store exiting yes Use TPR shadow yes NMI-window exiting no MOV-DR exiting yes Unconditional I/O exiting yes Use I/O bitmaps yes Monitor trap flag no Use MSR bitmaps yes MONITOR exiting yes PAUSE exiting yes Activate secondary control no secondary processor-based controls Virtualize APIC accesses no Enable EPT no Descriptor-table exiting no Enable RDTSCP no Virtualize x2APIC mode no Enable VPID no WBINVD exiting no Unrestricted guest no APIC register emulation no Virtual interrupt delivery no PAUSE-loop exiting no RDRAND exiting no Enable INVPCID no Enable VM functions no VMCS shadowing no Enable ENCLS exiting no RDSEED exiting no Enable PML no EPT-violation #VE no Conceal non-root operation from PT no Enable XSAVES/XRSTORS no Mode-based execute control (XS/XU) no TSC scaling no VM-Exit controls Save debug controls forced Host address-space size yes Load IA32_PERF_GLOBAL_CTRL no Acknowledge interrupt on exit yes Save IA32_PAT no Load IA32_PAT no Save IA32_EFER no Load IA32_EFER no Save VMX-preemption timer value no Clear IA32_BNDCFGS no Conceal VM exits from PT no VM-Entry controls Load debug controls forced IA-32e mode guest yes Entry to SMM yes Deactivate dual-monitor treatment yes Load IA32_PERF_GLOBAL_CTRL no Load IA32_PAT no Load IA32_EFER no Load IA32_BNDCFGS no Conceal VM entries from PT no Miscellaneous data Hex: 0x403c0 VMX-preemption timer scale (log2) 0 Store EFER.LMA into IA-32e mode guest control no HLT activity state yes Shutdown activity state yes Wait-for-SIPI activity state yes IA32_SMBASE support no Number of CR3-target values 4 MSR-load/store count recommendation 0 IA32_SMM_MONITOR_CTL[2] can be set to 1 no VMWRITE to VM-exit information fields no Inject event with insn length=0 no MSEG revision identifier 0 VPID and EPT capabilities Hex: 0x0 Execute-only EPT translations no Page-walk length 4 no Paging-structure memory type UC no Paging-structure memory type WB no 2MB EPT pages no 1GB EPT pages no INVEPT supported no EPT accessed and dirty flags no Single-context INVEPT no All-context INVEPT no INVVPID supported no Individual-address INVVPID no Single-context INVVPID no All-context INVVPID no Single-context-retaining-globals INVVPID no VM Functions Hex: 0x0 EPTP Switching no ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: kvm_intel fails to load on Conroe CPUs running Linux 4.12 2017-08-07 17:17 ` Sebastian Rachuj @ 2017-08-07 17:50 ` Paolo Bonzini 2017-08-07 18:43 ` Sebastian Rachuj 0 siblings, 1 reply; 13+ messages in thread From: Paolo Bonzini @ 2017-08-07 17:50 UTC (permalink / raw) To: Sebastian Rachuj, rkrcmar, tglx, mingo, hpa, x86, kvm, linux-kernel On 07/08/2017 19:17, Sebastian Rachuj wrote: >>> >>> Thank you for looking into the issue. My cpuinfo is as follows: >> >> Looks like Intel was already differentiating virtualization features >> across SKUs. Please run the attached script as root to see what other >> things are different (apparently) between non-Xeon and Xeon Conroes. > > Here you are, I hope it helps: Not much to say, unfortunately. It's pretty much the same capabilities as a Prescott/Cedar Mill processor, except that it has MSR bitmaps. It also lacks FlexPriority compared to the Conroe I had checked. It's not great that even the revert patch doesn't apply cleanly---this is *not* necessarily a boring area of the hypervisor... Given the rarity of your machine I'm currently leaning towards _not_ reverting the change. I'll check another non-Xeon Core 2 tomorrow that is from December 2008 (IIRC). If that one also lacks vNMI, or if I get other reports, I suppose I will have to reconsider that. Paolo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: kvm_intel fails to load on Conroe CPUs running Linux 4.12 2017-08-07 17:50 ` Paolo Bonzini @ 2017-08-07 18:43 ` Sebastian Rachuj 0 siblings, 0 replies; 13+ messages in thread From: Sebastian Rachuj @ 2017-08-07 18:43 UTC (permalink / raw) To: Paolo Bonzini, rkrcmar, tglx, mingo, hpa, x86, kvm, linux-kernel On 07.08.2017 19:50, Paolo Bonzini wrote: > On 07/08/2017 19:17, Sebastian Rachuj wrote: >>>> >>>> Thank you for looking into the issue. My cpuinfo is as follows: >>> >>> Looks like Intel was already differentiating virtualization features >>> across SKUs. Please run the attached script as root to see what other >>> things are different (apparently) between non-Xeon and Xeon Conroes. >> >> Here you are, I hope it helps: > > Not much to say, unfortunately. It's pretty much the same capabilities > as a Prescott/Cedar Mill processor, except that it has MSR bitmaps. It > also lacks FlexPriority compared to the Conroe I had checked. > > It's not great that even the revert patch doesn't apply cleanly---this > is *not* necessarily a boring area of the hypervisor... > > Given the rarity of your machine I'm currently leaning towards _not_ > reverting the change. I'll check another non-Xeon Core 2 tomorrow that > is from December 2008 (IIRC). If that one also lacks vNMI, or if I get > other reports, I suppose I will have to reconsider that. That's unfortunate to hear. Just for completeness, I want to mention a thread in the Archlinux forum, I created, where two other people (Sadar and losko) also complained about not working KVM [1]. Additionally, Linux 4.12 has not reached yet reached distributions with a greater amount of users. If supporting these chips is too much of a hassle, I will probably have to buy a new CPU to enjoy KVM support with a current linux kernel. Anyway, thanks again for figuring this out! [1]: https://bbs.archlinux.org/viewtopic.php?id=228645 ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2017-09-27 19:31 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
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2017-09-15 17:07 ` Paolo Bonzini
2017-09-27 19:31 ` Gerhard Wiesinger
2017-08-05 19:26 Sebastian Rachuj
2017-08-06 21:10 ` Paolo Bonzini
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2017-08-07 9:43 ` Paolo Bonzini
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2017-08-07 17:17 ` Sebastian Rachuj
2017-08-07 17:50 ` Paolo Bonzini
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