[PATCH v5 0/2] Add Agilex5 AXI DMA support

[PATCH v5 0/2] Add Agilex5 AXI DMA support

[Khairul Anuar Romli]

This series introduces support for Agilex5 SoC in the Synopsys DesignWare
AXI DMA binding and updates the device tree to use the platform-specific
compatible string.

The Agilex5 only has 40-bit DMA addressable bit instead of 64-bit. Hence,
this specific addition will enable driver to handle this limitation.

---
Notes:
This patch series is applied on socfpga maintainer's tree
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.20

Changes in v5:
	- Drop driver changes since Rob's comment that the core will merge the
          device's mask with the bus ranges.

Changes in v4:
	- Use common code to get dma ranges.
	- Simplify the code to only in hw_init that will set the bit mask.

Changes in v3:
	- simplify dma-ranges addition without description as per input
	  from Rob.
	- Add simple-bus to with address-cells, size-cells, dma-ranges
	  added under this bus-node.
	- Move dma controller device node under simple-bus node.
	- Rename "arm64: dts: intel: agilex5: Add dma-ranges, address and size
	  cells to dma node" to #2
	- Drop "dt-bindings: dma: snps,dw-axi-dmac: Add #address-cells and
	  #size-cells"
	- Refactor "dma: dw-axi-dmac: Add support for Agilex5 and dynamic bus
	  width" to align with dma controller node now under simple-bus node.

Changes in v2:
	- Add dma-ranges property.
	- Add address-cells and size-cells due to warning when dma-ranges
	  is define without address-cells and size-cells present. Also
	  prevent kernel panic if address-cells and size-cells are not
	  defined.
	- Add driver support to handle defined properties and set the DMA
	  BIT MASK according to value from DT.
	- Rename "arm64: dts: agilex5: Use platform-specific compatible for
          AXI DMA" to "arm64: dts: intel: agilex5: Add dma-ranges and
          address cells to dma node"

This changes is validated on:
	- intel/socfpga_agilex5_socdk.dtb
	- snps,dw-axi-dmac.yaml
	- snps,dw-axi-dmac.yaml intel/socfpga_agilex5_socdk.dtb
	- Agilex5 devkit
---
Khairul Anuar Romli (2):
  dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5
  arm64: dts: intel: agilex5: Add simple-bus node on top of dma
    controller node

 .../bindings/dma/snps,dw-axi-dmac.yaml        | 14 ++--
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 78 ++++++++++---------
 2 files changed, 52 insertions(+), 40 deletions(-)

-- 
2.43.7

[PATCH v5 1/2] dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5

[Khairul Anuar Romli]

The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this
will cause address truncation and translation faults. Hence introducing
"altr,agilex5-axi-dma" to enable platform specific configuration to
configure the dma addressable bit mask.

Add a fallback capability for the compatible property to allow driver to
probe and initialize with a newly added compatible string without requiring
additional entry in the driver.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v5:
	- No changes
Changes in v4:
	- remove dma-ranges as it is no longer required
Changes in v3:
	- Simple dma-ranges property with true and without description
Changes in v2:
	- Add dma-ranges
---
 .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml  | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index eb67348b4ab1..e12a48a12ea4 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -17,11 +17,15 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - snps,axi-dma-1.01a
-      - intel,kmb-axi-dma
-      - starfive,jh7110-axi-dma
-      - starfive,jh8100-axi-dma
+    oneOf:
+      - enum:
+          - snps,axi-dma-1.01a
+          - intel,kmb-axi-dma
+          - starfive,jh7110-axi-dma
+          - starfive,jh8100-axi-dma
+      - items:
+          - const: altr,agilex5-axi-dma
+          - const: snps,axi-dma-1.01a
 
   reg:
     minItems: 1
-- 
2.43.7

[PATCH v5 2/2] arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node

[Khairul Anuar Romli]

Move dma-controller node under simple-bus node to allow bus node specific
property able to be properly defined. This is require to fulfill Agilex5
bus limitation that is limited to 40-addressable-bit.

Update the compatible string for the DMA controller nodes in the Agilex5
device tree from the generic "snps,axi-dma-1.01a" to the platform-specific
"altr,agilex5-axi-dma". Add fallback capability to ensure driver is able
to initialize properly.

This change enables the use of platform-specific features and constraints
in the driver, such as setting a 40-bit DMA addressable mask through
dma-ranges, which is required for Agilex5. It also aligns with the updated
device tree bindings and driver support for this compatible string.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v5:
	- No changes.
Changes in v4:
	- No changes.
Changes in v3:
	- Rename the patch  "arm64: dts: intel: agilex5: Add dma-ranges, address
	  and size cells to dma node"
	- Add simple-bus and move dmac0 and dmac1 1 level down.
Changes in v2:
	- Rename the from add platform specific to add dma-ranges, address
	  and size cells.
	- Define address-cells and size-cells for dmac0 and dmac1
	- Add dma-ranges for agilex5 for 40-bit
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 78 ++++++++++---------
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 78 ++++++++++---------
 1 file changed, 43 insertions(+), 35 deletions(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index db8d5c426821..2d8ce64e2388 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -324,42 +324,50 @@ ocram: sram@0 {
 			#size-cells = <1>;
 		};
 
-		dmac0: dma-controller@10db0000 {
-			compatible = "snps,axi-dma-1.01a";
-			reg = <0x10db0000 0x500>;
-			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
-				 <&clkmgr AGILEX5_L4_MP_CLK>;
-			clock-names = "core-clk", "cfgr-clk";
-			interrupt-parent = <&intc>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			#dma-cells = <1>;
-			dma-channels = <4>;
-			snps,dma-masters = <1>;
-			snps,data-width = <2>;
-			snps,block-size = <32767 32767 32767 32767>;
-			snps,priority = <0 1 2 3>;
-			snps,axi-max-burst-len = <8>;
-			iommus = <&smmu 8>;
-			dma-coherent;
-		};
+		dma: dma-bus@10db0000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <2>;
+			ranges = <0x00 0x10db0000 0x00 0x20000>;
+			dma-ranges = <0x00 0x00 0x100 0x00>;
+
+			dmac0: dma-controller@0 {
+				compatible = "altr,agilex5-axi-dma",
+					     "snps,axi-dma-1.01a";
+				reg = <0x0 0x0 0x500>;
+				clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
+					 <&clkmgr AGILEX5_L4_MP_CLK>;
+				clock-names = "core-clk", "cfgr-clk";
+				interrupt-parent = <&intc>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				#dma-cells = <1>;
+				dma-channels = <4>;
+				snps,dma-masters = <1>;
+				snps,data-width = <2>;
+				snps,block-size = <32767 32767 32767 32767>;
+				snps,priority = <0 1 2 3>;
+				snps,axi-max-burst-len = <8>;
+				iommus = <&smmu 8>;
+			};
 
-		dmac1: dma-controller@10dc0000 {
-			compatible = "snps,axi-dma-1.01a";
-			reg = <0x10dc0000 0x500>;
-			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
-				 <&clkmgr AGILEX5_L4_MP_CLK>;
-			clock-names = "core-clk", "cfgr-clk";
-			interrupt-parent = <&intc>;
-			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
-			#dma-cells = <1>;
-			dma-channels = <4>;
-			snps,dma-masters = <1>;
-			snps,data-width = <2>;
-			snps,block-size = <32767 32767 32767 32767>;
-			snps,priority = <0 1 2 3>;
-			snps,axi-max-burst-len = <8>;
-			iommus = <&smmu 9>;
-			dma-coherent;
+			dmac1: dma-controller@10000 {
+				compatible = "altr,agilex5-axi-dma",
+					     "snps,axi-dma-1.01a";
+				reg = <0x10000 0x0 0x500>;
+				clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
+					 <&clkmgr AGILEX5_L4_MP_CLK>;
+				clock-names = "core-clk", "cfgr-clk";
+				interrupt-parent = <&intc>;
+				interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+				#dma-cells = <1>;
+				dma-channels = <4>;
+				snps,dma-masters = <1>;
+				snps,data-width = <2>;
+				snps,block-size = <32767 32767 32767 32767>;
+				snps,priority = <0 1 2 3>;
+				snps,axi-max-burst-len = <8>;
+				iommus = <&smmu 9>;
+			};
 		};
 
 		rst: rstmgr@10d11000 {
-- 
2.43.7

Re: [PATCH v5 1/2] dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5

[Rob Herring (Arm)]

On Mon, 29 Dec 2025 11:49:01 +0800, Khairul Anuar Romli wrote:
> The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this
> will cause address truncation and translation faults. Hence introducing
> "altr,agilex5-axi-dma" to enable platform specific configuration to
> configure the dma addressable bit mask.
> 
> Add a fallback capability for the compatible property to allow driver to
> probe and initialize with a newly added compatible string without requiring
> additional entry in the driver.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v5:
> 	- No changes
> Changes in v4:
> 	- remove dma-ranges as it is no longer required
> Changes in v3:
> 	- Simple dma-ranges property with true and without description
> Changes in v2:
> 	- Add dma-ranges
> ---
>  .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml  | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: (subset) [PATCH v5 0/2] Add Agilex5 AXI DMA support

[Vinod Koul]

On Mon, 29 Dec 2025 11:49:00 +0800, Khairul Anuar Romli wrote:
> This series introduces support for Agilex5 SoC in the Synopsys DesignWare
> AXI DMA binding and updates the device tree to use the platform-specific
> compatible string.
> 
> The Agilex5 only has 40-bit DMA addressable bit instead of 64-bit. Hence,
> this specific addition will enable driver to handle this limitation.
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5
      commit: 0a6946644f0d1151d31212820497e1a49fe1a0a6

Best regards,
-- 
~Vinod

Re: (subset) [PATCH v5 0/2] Add Agilex5 AXI DMA support

[Romli, Khairul Anuar]

On 2/1/2026 1:41 am, Vinod Koul wrote:
> 
> On Mon, 29 Dec 2025 11:49:00 +0800, Khairul Anuar Romli wrote:
>> This series introduces support for Agilex5 SoC in the Synopsys DesignWare
>> AXI DMA binding and updates the device tree to use the platform-specific
>> compatible string.
>>
>> The Agilex5 only has 40-bit DMA addressable bit instead of 64-bit. Hence,
>> this specific addition will enable driver to handle this limitation.
>>
>> [...]
> 
> Applied, thanks!
> 
> [1/2] dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5
>        commit: 0a6946644f0d1151d31212820497e1a49fe1a0a6
> 
> Best regards,

Thank you so much for getting this patch series reviewed and accepted.

Regards,
Khairul

Re: [PATCH v5 2/2] arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node

[Dinh Nguyen]

On 12/28/25 21:49, Khairul Anuar Romli wrote:
> Move dma-controller node under simple-bus node to allow bus node specific
> property able to be properly defined. This is require to fulfill Agilex5
> bus limitation that is limited to 40-addressable-bit.
> 
> Update the compatible string for the DMA controller nodes in the Agilex5
> device tree from the generic "snps,axi-dma-1.01a" to the platform-specific
> "altr,agilex5-axi-dma". Add fallback capability to ensure driver is able
> to initialize properly.
> 
> This change enables the use of platform-specific features and constraints
> in the driver, such as setting a 40-bit DMA addressable mask through
> dma-ranges, which is required for Agilex5. It also aligns with the updated
> device tree bindings and driver support for this compatible string.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v5:
> 	- No changes.
> Changes in v4:
> 	- No changes.
> Changes in v3:
> 	- Rename the patch  "arm64: dts: intel: agilex5: Add dma-ranges, address
> 	  and size cells to dma node"
> 	- Add simple-bus and move dmac0 and dmac1 1 level down.
> Changes in v2:
> 	- Rename the from add platform specific to add dma-ranges, address
> 	  and size cells.
> 	- Define address-cells and size-cells for dmac0 and dmac1
> 	- Add dma-ranges for agilex5 for 40-bit
> ---
>   .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 78 ++++++++++---------
>   .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 78 ++++++++++---------
>   1 file changed, 43 insertions(+), 35 deletions(-)
> 

Applied!

Thanks,
Dinh