[PATCH 0/2] arm64: dts: intel: fix dw-apb-timer clock initialisation on Agilex and Agilex5

[PATCH 0/2] arm64: dts: intel: fix dw-apb-timer clock initialisation on Agilex and Agilex5

[Adrian Ng Ho Yin]

The DesignWare APB timers on Intel Agilex and Agilex5 SoCs fail to
initialise because their clock managers are platform drivers registered
at core_initcall, which runs after time_init() where TIMER_OF_DECLARE
callbacks fire.  With clocks/clock-names in the DTS, the timer driver
calls clk_get() at a point when the clock provider is not yet
registered, causing the timers to never come up.

Replace the clocks/clock-names reference in both DTSIs with a static
clock-frequency of 100 MHz, which is the L4_SP clock rate configured
by the bootloader.  The dw-apb-timer binding explicitly supports this
as an alternative when the clock framework is unavailable at probe time.

Adrian Ng Ho Yin (2):
  arm64: dts: socfpga: agilex5: replace clocks reference with
    clock-frequency for dw-apb-timer
  arm64: dts: socfpga: agilex: replace clocks reference with
    clock-frequency for dw-apb-timer

 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi  | 12 ++++--------
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++--------
 2 files changed, 8 insertions(+), 16 deletions(-)

-- 
2.49.GIT

[PATCH 1/2] arm64: dts: socfpga: agilex5: replace clocks reference with clock-frequency for dw-apb-timer

[Adrian Ng Ho Yin]

The Agilex5 clock manager is a platform driver initialised at
core_initcall, after time_init() where TIMER_OF_DECLARE callbacks run.
The timer cannot defer its probe, so clk_get() fails and the timer is
never brought up.

With clock-frequency, the tick rate is read directly from the DT node
without involving the clock framework, allowing the timer to initialise
regardless of when the clock manager is ready.

Replace clocks/clock-names with a static clock-frequency of 100 MHz,
which is the L4_SP clock rate configured by the bootloader.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index b06c6d5d60ee..24b4d129b1d5 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -430,32 +430,28 @@ timer0: timer0@10c03000 {
 			compatible = "snps,dw-apb-timer";
 			reg = <0x10c03000 0x100>;
 			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
-			clock-names = "timer";
+			clock-frequency = <100000000>;
 		};
 
 		timer1: timer1@10c03100 {
 			compatible = "snps,dw-apb-timer";
 			reg = <0x10c03100 0x100>;
 			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
-			clock-names = "timer";
+			clock-frequency = <100000000>;
 		};
 
 		timer2: timer2@10d00000 {
 			compatible = "snps,dw-apb-timer";
 			reg = <0x10d00000 0x100>;
 			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
-			clock-names = "timer";
+			clock-frequency = <100000000>;
 		};
 
 		timer3: timer3@10d00100 {
 			compatible = "snps,dw-apb-timer";
 			reg = <0x10d00100 0x100>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
-			clock-names = "timer";
+			clock-frequency = <100000000>;
 		};
 
 		uart0: serial@10c02000 {
-- 
2.49.GIT

[PATCH 2/2] arm64: dts: socfpga: agilex: replace clocks reference with clock-frequency for dw-apb-timer

[Adrian Ng Ho Yin]

The Agilex clock manager is a platform driver initialised at
core_initcall, after time_init() where TIMER_OF_DECLARE callbacks run.
The timer cannot defer its probe, so clk_get() fails and the timer is
never brought up.

With clock-frequency, the tick rate is read directly from the DT node
without involving the clock framework, allowing the timer to initialise
regardless of when the clock manager is ready.

Replace clocks/clock-names with a static clock-frequency of 100 MHz,
which is the L4_SP clock rate configured by the bootloader.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 0dfbafde8822..4ed762c6e07f 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -491,32 +491,28 @@ timer0: timer0@ffc03000 {
 			compatible = "snps,dw-apb-timer";
 			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0xffc03000 0x100>;
-			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
-			clock-names = "timer";
+			clock-frequency = <100000000>;
 		};
 
 		timer1: timer1@ffc03100 {
 			compatible = "snps,dw-apb-timer";
 			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0xffc03100 0x100>;
-			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
-			clock-names = "timer";
+			clock-frequency = <100000000>;
 		};
 
 		timer2: timer2@ffd00000 {
 			compatible = "snps,dw-apb-timer";
 			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0xffd00000 0x100>;
-			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
-			clock-names = "timer";
+			clock-frequency = <100000000>;
 		};
 
 		timer3: timer3@ffd00100 {
 			compatible = "snps,dw-apb-timer";
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0xffd00100 0x100>;
-			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
-			clock-names = "timer";
+			clock-frequency = <100000000>;
 		};
 
 		uart0: serial@ffc02000 {
-- 
2.49.GIT