[PATCH 0/6] arm64: dts: socfpga: enable SD UHS and eMMC DDR modes on Agilex5/Agilex3 SoCDK

[tze.yee.ng@altera.com]

From: Tze Yee Ng <tze.yee.ng@altera.com>

This series enables higher-speed SD/MMC modes on the Agilex5 and Agilex3
SoC development kits.

Patch 1 adds the shared DDR50 read-path tuning defaults to the Agilex5
sdmmc node (also inherited by Agilex3). Patches 2-3 enable SD DDR50 and
1.8V eMMC DDR on the Agilex5 SoCDK. Patches 4-6 bring up the micro-SD
slot (regulators + SDR104/DDR50) on the Agilex5 SoCDK modular, Agilex5
SoCDK 013B and Agilex3 SoCDK.

Depends on the SD6HC DDR read-path tuning series [1], which adds the
sdhci-cadence driver and the dt-bindings for the cdns,ddr50-* properties
used here; please apply it first.

[1] https://lore.kernel.org/all/cover.1790074790.git.tze.yee.ng@altera.com/

Tze Yee Ng (6):
  arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc
  arm64: dts: socfpga: agilex5: enable SD UHS DDR50 on SoCDK
  arm64: dts: socfpga: agilex5: enable eMMC 1.8V DDR on SoCDK eMMC
  arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular
  arm64: dts: socfpga: agilex5: enable SD card on SoCDK 013B
  arm64: dts: socfpga: agilex3: enable SD card on SoCDK

 .../boot/dts/intel/socfpga_agilex3_socdk.dts  | 33 ++++++++++++++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  2 +
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  1 +
 .../dts/intel/socfpga_agilex5_socdk_013b.dts  | 33 ++++++++++++++
 .../dts/intel/socfpga_agilex5_socdk_emmc.dts  |  1 +
 .../intel/socfpga_agilex5_socdk_modular.dts   | 44 +++++++++++++++++++
 6 files changed, 114 insertions(+)

-- 
2.43.7