[PATCH 0/6] arm64: dts: socfpga: enable SD UHS and eMMC DDR modes on Agilex5/Agilex3 SoCDK

[PATCH 0/6] arm64: dts: socfpga: enable SD UHS and eMMC DDR modes on Agilex5/Agilex3 SoCDK

[tze.yee.ng]

From: Tze Yee Ng <tze.yee.ng@altera.com>

This series enables higher-speed SD/MMC modes on the Agilex5 and Agilex3
SoC development kits.

Patch 1 adds the shared DDR50 read-path tuning defaults to the Agilex5
sdmmc node (also inherited by Agilex3). Patches 2-3 enable SD DDR50 and
1.8V eMMC DDR on the Agilex5 SoCDK. Patches 4-6 bring up the micro-SD
slot (regulators + SDR104/DDR50) on the Agilex5 SoCDK modular, Agilex5
SoCDK 013B and Agilex3 SoCDK.

Depends on the SD6HC DDR read-path tuning series [1], which adds the
sdhci-cadence driver and the dt-bindings for the cdns,ddr50-* properties
used here; please apply it first.

[1] https://lore.kernel.org/all/cover.1790074790.git.tze.yee.ng@altera.com/

Tze Yee Ng (6):
  arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc
  arm64: dts: socfpga: agilex5: enable SD UHS DDR50 on SoCDK
  arm64: dts: socfpga: agilex5: enable eMMC 1.8V DDR on SoCDK eMMC
  arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular
  arm64: dts: socfpga: agilex5: enable SD card on SoCDK 013B
  arm64: dts: socfpga: agilex3: enable SD card on SoCDK

 .../boot/dts/intel/socfpga_agilex3_socdk.dts  | 33 ++++++++++++++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  2 +
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  1 +
 .../dts/intel/socfpga_agilex5_socdk_013b.dts  | 33 ++++++++++++++
 .../dts/intel/socfpga_agilex5_socdk_emmc.dts  |  1 +
 .../intel/socfpga_agilex5_socdk_modular.dts   | 44 +++++++++++++++++++
 6 files changed, 114 insertions(+)

-- 
2.43.7

[PATCH 1/6] arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc

[tze.yee.ng]

From: Tze Yee Ng <tze.yee.ng@altera.com>

Add the Cadence SD6HC DDR50 read-path tuning properties to the shared
Agilex5 sdmmc node so that boards enabling SD UHS DDR50 pick up sane
defaults for the loopback DQS selection and the read DQS delay:

  - cdns,ddr50-use-lpbk-dqs = <0>
  - cdns,ddr50-read-dqs-delay = <96>

Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 5f22e6d7ab85..dc25b7382a29 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -322,6 +322,8 @@ sdmmc: mmc@10808000 {
 			resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>,
 				 <&rst SDMMC_OCP_RESET>;
 			reset-names = "sdhc-reset", "combophy", "sdmmc-ocp";
+			cdns,ddr50-use-lpbk-dqs = <0>;
+			cdns,ddr50-read-dqs-delay = <96>;
 
 			status = "disabled";
 		};
-- 
2.43.7

[PATCH 2/6] arm64: dts: socfpga: agilex5: enable SD UHS DDR50 on SoCDK

[tze.yee.ng]

From: Tze Yee Ng <tze.yee.ng@altera.com>

The SoCDK SD interface already advertises SDR104. Add sd-uhs-ddr50 so
the DDR50 UHS-I mode is available as well, using the DDR50 read-path
tuning defaults from the SoC dtsi.

Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index bc5b7956a720..8a22b05315a5 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -63,6 +63,7 @@ &sdmmc {
 	disable-wp;
 	max-frequency = <200000000>;
 	no-mmc;
+	sd-uhs-ddr50;
 	sd-uhs-sdr104;
 	vmmc-supply = <&vmmc_reg>;
 	vqmmc-supply = <&vqmmc_io_reg>;
-- 
2.43.7

[PATCH 3/6] arm64: dts: socfpga: agilex5: enable eMMC 1.8V DDR on SoCDK eMMC

[tze.yee.ng]

From: Tze Yee Ng <tze.yee.ng@altera.com>

Add mmc-ddr-1_8v to the eMMC variant so the controller can use the
high-speed DDR (52 MHz) 1.8V eMMC mode in addition to the existing
HS200/HS400 modes.

Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts
index beb4f444c471..52e3eeb98e8a 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts
@@ -63,6 +63,7 @@ &sdmmc {
 	max-frequency = <200000000>;
 	mmc-hs200-1_8v;
 	mmc-hs400-1_8v;
+	mmc-ddr-1_8v;
 	no-sd;
 	no-sdio;
 	non-removable;
-- 
2.43.7

[PATCH 4/6] arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular

[tze.yee.ng]

From: Tze Yee Ng <tze.yee.ng@altera.com>

Enable the micro-SD slot on the Agilex5 SoCDK modular board:

  - Add the fixed 3.3V card supply and the GPIO-controlled 1.8V/3.3V
    VQMMC I/O regulator driven by the on-SoM PCA9535 expander.
  - Enable the I2C3 bus and describe the PCA9535 expander that gates
    the SD I/O voltage switch.
  - Enable the sdmmc node in 4-bit mode with SDR104 and DDR50 UHS-I
    support, wire up the vmmc/vqmmc supplies, and set the board's
    DDR50 phony DQS timing.

Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
---
 .../intel/socfpga_agilex5_socdk_modular.dts   | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
index a2b707ae6e9e..7b44c24412c2 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
@@ -34,6 +34,24 @@ memory@80000000 {
 		/* We expect the bootloader to fill in the reg */
 		reg = <0x0 0x80000000 0x0 0x0>;
 	};
+
+	vqmmc_io_reg: regulator-1p8v {
+		compatible = "regulator-gpio";
+		regulator-name = "sd-bus-io-power";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		gpios = <&expander1 1 GPIO_ACTIVE_HIGH>;
+		states = <1800000 0x1>,
+			 <3300000 0x0>;
+	};
+
+	vmmc_reg: regulator-fixed-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "card-power";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
 };
 
 &gpio0 {
@@ -61,6 +79,32 @@ emac2_phy0: ethernet-phy@0 {
 	};
 };
 
+&i2c3 {
+	status = "okay";
+
+	expander1: gpio@27 {
+		compatible = "nxp,pca9535";
+		reg = <0x27>;			/* SoM expander address */
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <200000000>;
+	no-mmc;
+	sd-uhs-ddr50;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vmmc_reg>;
+	vqmmc-supply = <&vqmmc_io_reg>;
+	cdns,ddr50-phony-dqs-timing = <0>;
+
+	status = "okay";
+};
+
 &osc1 {
 	clock-frequency = <25000000>;
 };
-- 
2.43.7

[PATCH 5/6] arm64: dts: socfpga: agilex5: enable SD card on SoCDK 013B

[tze.yee.ng]

From: Tze Yee Ng <tze.yee.ng@altera.com>

Enable the micro-SD slot on the Agilex5 SoCDK 013B board:

  - Add the fixed 3.3V card supply and the GPIO-controlled 1.8V/3.3V
    VQMMC I/O regulator.
  - Enable the sdmmc node in 4-bit mode with SDR104 and DDR50 UHS-I
    support and wire up the vmmc/vqmmc supplies.

Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
---
 .../dts/intel/socfpga_agilex5_socdk_013b.dts  | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
index 1e946d5765e0..6b927b35a9dc 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
@@ -39,6 +39,25 @@ memory@80000000 {
 		/* We expect the bootloader to fill in the reg */
 		reg = <0x0 0x80000000 0x0 0x0>;
 	};
+
+	vqmmc_io_reg: regulator-1p8v {
+		compatible = "regulator-gpio";
+		gpios = <&portb 3 GPIO_ACTIVE_HIGH>;
+		gpios-states = <0>;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "vqmmc-io";
+		states = <1800000 0x1>,
+			 <3300000 0x0>;
+	};
+
+	vmmc_reg: regulator-fixed-3p3v {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "vcc-sd";
+	};
 };
 
 &gmac2 {
@@ -115,6 +134,20 @@ root: partition@c00000 {
 	};
 };
 
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <200000000>;
+	no-mmc;
+	sd-uhs-ddr50;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vmmc_reg>;
+	vqmmc-supply = <&vqmmc_io_reg>;
+
+	status = "okay";
+};
+
 &smmu {
 	status = "okay";
 };
-- 
2.43.7

[PATCH 6/6] arm64: dts: socfpga: agilex3: enable SD card on SoCDK

[tze.yee.ng]

From: Tze Yee Ng <tze.yee.ng@altera.com>

Enable the micro-SD slot on the Agilex3 SoCDK board:

  - Add the fixed 3.3V card supply and the GPIO-controlled 1.8V/3.3V
    VQMMC I/O regulator.
  - Enable the sdmmc node in 4-bit mode with SDR104 and DDR50 UHS-I
    support and wire up the vmmc/vqmmc supplies.

The board includes socfpga_agilex5.dtsi, so the DDR50 read-path tuning
defaults added there apply here as well.

Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
---
 .../boot/dts/intel/socfpga_agilex3_socdk.dts  | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
index b40f28519334..f46e5c070c0e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
@@ -45,6 +45,25 @@ memory@80000000 {
 		/* We expect the bootloader to fill in the reg */
 		reg = <0x0 0x80000000 0x0 0x0>;
 	};
+
+	vqmmc_io_reg: regulator-1p8v {
+		compatible = "regulator-gpio";
+		gpios = <&portb 3 GPIO_ACTIVE_HIGH>;
+		gpios-states = <0>;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "vqmmc-io";
+		states = <1800000 0x1>,
+			 <3300000 0x0>;
+	};
+
+	vmmc_reg: regulator-fixed-3p3v {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "vcc-sd";
+	};
 };
 
 &gmac2 {
@@ -121,6 +140,20 @@ root: partition@c00000 {
 	};
 };
 
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <200000000>;
+	no-mmc;
+	sd-uhs-ddr50;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vmmc_reg>;
+	vqmmc-supply = <&vqmmc_io_reg>;
+
+	status = "okay";
+};
+
 &smmu {
 	status = "okay";
 };
-- 
2.43.7