Re: [PATCH 0/9] Intel Processor Trace virtulization enabling

[Paolo Bonzini <pbonzini@redhat.com>]

On 19/10/2017 07:54, Kang, Luwei wrote:
>>> Get it. I have feedback to hardware architect. I hope it can be applied but it may need wait a long time.
>> Note that the hardware need not do anything.  However it would be nice if the SDM can define a bit _for the hypervisors_ to
>> enforce the above constraint and fail vmentry if they are not respected.
>
> Hi Paolo,
> Thanks for your response. I have a question want to ask for you. As
> you mentioned in previous mail " We would like the nested hypervisor
> to be forced to set the "use GPA for processor tracing"". Is there
> have any problem if we don't set "use GPA for processor tracing" in
> nested hypervisor?

If the nested hypervisor doesn't set "use GPA for processor tracing",
the processor should use L1 addresses for processor tracing.  This
however is not possible without shadowing the ToPA, same as in
non-nested virtualization for <=Skylake processors.

So we have

            |          mode
            |-----------------------------------------------------------
nested?     |          system-wide          |  host-guest
------------+-------------------------------+---------------------------
no          |          use HPA for tracing  |  use GPA for tracing
            |          (no EPT)             |  (EPT is GPA->HPA)
------------+-------------------------------+---------------------------
yes         |          use GPA for tracing  |  use nGPA for tracing
            |          (EPT is nGPA->HPA!!) |  (EPT is nGPA->HPA, so ok)

(for nested, L0 mode of course must be host-guest).  If the nested
hypervisor wants to use system-wide tracing, it cannot use "use GPA for
tracing" because the EPT table doesn't have the right mapping of L1->L0
physical address.

So if you want to do system-wide L1 tracing you have to disable EPT for
L1, and if you want to do host-guest L1 tracing you have to enable it.

Paolo

> If yes, what should we do? In patch 9, I pass
> though PT MSRs ( IA32_RTIT_* ) to guest.